Table 1 Implementation results.
Number of slices | 138 out of 2352 5% |
|---|---|
Number of slice flip flops | 232 out of 4704 4% |
Number of 4 input LUTs | 86 out of 4704 1% |
Max. clock frequency | 100.675 MHz |
Number of slices | 138 out of 2352 5% |
|---|---|
Number of slice flip flops | 232 out of 4704 4% |
Number of 4 input LUTs | 86 out of 4704 1% |
Max. clock frequency | 100.675 MHz |