Table 1 Characteristics of different transceiver simulation models.

Floating-point/SW Simulation

Fast (runtime)

Algorithm development

Far from hardware (HW) (data and control path)

Reference for other models

Fixed-point/SW Simulation

Slow (runtime)

Golden model for HDL

Same data path as HW

Debug data path

Different control path

Not cycle-true

HDL/Simulator

Slow (runtime)

Debug control path

Data and control path as in final ASIC

Cycle-accurate: determine latencies

HDL/FPGA

Fast (runtime)

Performance, fixed-point characterization

Accelerated HDL simulation

Large coverage of functional runs

Regression runs