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  • Research Article
  • Open Access

Reconfigurable Signal Processing and Hardware Architecture for Broadband Wireless Communications

  • 1Email author,
  • 1,
  • 1 and
  • 1
EURASIP Journal on Wireless Communications and Networking20052005:871962

https://doi.org/10.1155/WCN.2005.323

  • Received: 1 October 2004
  • Published:

Abstract

This paper proposes a broadband wireless transceiver which can be reconfigured to any type of cyclic-prefix (CP) -based communication systems, including orthogonal frequency-division multiplexing (OFDM), single-carrier cyclic-prefix (SCCP) system, multicarrier (MC) code-division multiple access (MC-CDMA), MC direct-sequence CDMA (MC-DS-CDMA), CP-based CDMA (CP-CDMA), and CP-based direct-sequence CDMA (CP-DS-CDMA). A hardware platform is proposed and the reusable common blocks in such a transceiver are identified. The emphasis is on the equalizer design for mobile receivers. It is found that after block despreading operation, MC-DS-CDMA and CP-DS-CDMA have the same equalization blocks as OFDM and SCCP systems, respectively, therefore hardware and software sharing is possible for these systems. An attempt has also been made to map the functional reconfigurable transceiver onto the proposed hardware platform. The different functional entities which will be required to perform the reconfiguration and realize the transceiver are explained.

Keywords

  • reconfigurable signal processing
  • broadband communications
  • software-defined radio
  • cyclic prefix
  • frequency-domain equalization

Authors’ Affiliations

(1)
Institute for InfoComm Research (I2R), 21 Heng Mui Keng Terrace, 119613, Singapore

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