Skip to content


  • Research Article
  • Open Access

Reconfigurable Signal Processing and Hardware Architecture for Broadband Wireless Communications

  • Ying-Chang Liang1Email author,
  • Sayed Naveen1,
  • Santosh K Pilakkat1 and
  • Ashok K Marath1
EURASIP Journal on Wireless Communications and Networking20052005:871962

Received: 1 October 2004

Published: 1 August 2005


This paper proposes a broadband wireless transceiver which can be reconfigured to any type of cyclic-prefix (CP) -based communication systems, including orthogonal frequency-division multiplexing (OFDM), single-carrier cyclic-prefix (SCCP) system, multicarrier (MC) code-division multiple access (MC-CDMA), MC direct-sequence CDMA (MC-DS-CDMA), CP-based CDMA (CP-CDMA), and CP-based direct-sequence CDMA (CP-DS-CDMA). A hardware platform is proposed and the reusable common blocks in such a transceiver are identified. The emphasis is on the equalizer design for mobile receivers. It is found that after block despreading operation, MC-DS-CDMA and CP-DS-CDMA have the same equalization blocks as OFDM and SCCP systems, respectively, therefore hardware and software sharing is possible for these systems. An attempt has also been made to map the functional reconfigurable transceiver onto the proposed hardware platform. The different functional entities which will be required to perform the reconfiguration and realize the transceiver are explained.


reconfigurable signal processingbroadband communicationssoftware-defined radiocyclic prefixfrequency-domain equalization

Authors’ Affiliations

Institute for InfoComm Research (I2R), Singapore


© Ying-Chang Liang et al. 2005

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.