Open Access

Extended Lock Range Zero-Crossing Digital Phase-Locked Loop with Time Delay

EURASIP Journal on Wireless Communications and Networking20052005:389793

https://doi.org/10.1155/WCN.2005.413

Received: 7 November 2004

Published: 1 August 2005

Abstract

The input frequency limit of the conventional zero-crossing digital phase-locked loop (ZCDPLL) is due to the operating time of the digital circuitry inside the feedback loop. A solution that has been previously suggested is the introduction of a time delay in the feedback path of the loop to allow the digital circuits to complete their sample processing before the next sample is received. However, this added delay will limit the stable operation range and hence lock range of the loop. The objective of this work is to extend the lock range of ZCDPLL with time delay by using a chaos control. The tendency of the loop to diverge is measured and fed back as a form of linear stabilization. The lock range extension has been confirmed through the use of a bifurcation diagram, and Lyapunov exponent.

Keywords

nonuniform samplingdigital phase locked loopschaos control

Authors’ Affiliations

(1)
Department of Electrical and Computer Engineering, College of Engineering, University of Sharjah

Copyright

© Qassim Nasir 2005

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.