Table 4 Synthesis results
From: An adaptive low-power LDPC decoder using SNR estimation
Technology | Chartered 0.18 μm CMOS |
|---|---|
LDPC total (in NAND2) | 256 K |
AGU (in NAND2, with memory) | 82 K |
Parity check (in NAND2) | 1 K |
Tentative (in NAND2) | 1 K |
SNR estimator (in NAND2) | 31 K |
Operating freq. (MHz) | 188 |
Voltage (V) | 1.8 |