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Table 4 1-D Memory mapping and synthesis result of design example

From: Non-volatile memory reduction based on 1-D memory space mapping of a specific set of QC-LDPC codes

H-matrix

Type

Non-zero elements storage (M × k × Z)

Multiple constructions

1-D memory mapping

   

( N , j , k )

Rate

p

( j + k-1 ) z

Reduction factor

H1

MWC-OCS

724 × 8 × 11 = 63712 bits

(1448,4,8)

0.5A

181

11 × 8 = 88 bits

1.38 × 10-3

H2

MWC-OCS

3508 × 8 × 13 = 364832 bits

(7016,4,8)

0.5B

877

11 × 10 = 110 bits

3.01 × 10-4

H3

MWC-OCS

412 × 16 × 11 = 72512 bits

(1648,4,16)

0.75A

103

19 × 7 = 133 bits

1.83 × 10-3

H4

MWC-OCS

1004 × 16 × 12 = 192768 bits

(4016,4,16)

0.75B

251

19 × 8 = 152 bits

7.88 × 10-4

H-library

MWC-OCS

693824 bits

   

483 bits

6.96 × 10-4

Preprocess

MWC-OCS

693824 bits

   

348 bits

5.02 × 10-4

Synthesis results

MWC-OCS H-library

152 output pads (memory less and gate free)

13 gates (non-volatile)

16 DFFs (volatile)