Table 1 Features of reconfigurable Benes network
From: Systematic construction, verification and implementation methodology for LDPC codes
Scale | W = 9, S = 256, 15 stages, 128 × 15 MUX |
|---|---|
Support | p = 64:8:256, 1 ≤ c ≤ p |
Resource | 20866 LE, 388 memory bits |
Clock | 100 MHz for Cyclone II, 240 MHz for Stratix III |
Delay | Two clocks for control signals, four clocks for output |