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Table 4 Features of the multi-mode high-throughput decoder

From: Systematic construction, verification and implementation methodology for LDPC codes

FPGA platform Altera Stratix III EP3SL340F1517C2
Decoding scheme Layered offset-threshold MSA
Modes supported 9 × 3 = 27 modes
Code length N = 1536:768:6144 (z f = 64:32:256)
Code rate R = 1/ 2,2/ 3,3/ 4 (Hb:12 × 24, 8 × 24, 6 × 24)
Iteration number iter = 1−31, 20 recommended
Resources usage 149, 976 LE, 3, 157, 136 bits memory
BER performance gap 0.2 dB vs. 20 iteration float LMMSA
Clock setup 225.58MHz
Stable net throughput 721.58 Mbps (z f = 256, R = 1/ 2, iter = 20)
Max. net throughput 1.2 Gbps (early-stopping, iter = 12 ave.)