Figure 7
From: Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design
Decoding performance. (a) Throughput performance for normal frame DVB-S2 codes with P = {45, 90, 180, 360} FUs performing ten iterations; (b) throughput performance for short frame DVB-S2 codes with P = {45, 90, 180, 360} FUs performing ten iterations; (c) maximum number of iterations for normal frame DVB-S2 codes with P = {45, 90, 180, 360} FUs for a 90 Mbps throughput; (d) maximum number of iterations for short frame DVB-S2 codes with P = {45, 90, 180, 360} FUs for a 90 Mbps throughput.