From: Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design
Rate | Codeword bits (N) | Inf. bits (K) | Col. weight (w b ) | Row weight (w c ) | Number of edges |
---|---|---|---|---|---|
1/4 | 64800 | 16200 | {3, 12} | {4} | 194400 |
1/3 | 64800 | 21600 | {3, 12} | {5} | 216000 |
2/5 | 64800 | 25920 | {3, 12} | {6} | 233280 |
1/2 | 64800 | 32400 | {3, 8} | {7} | 226800 |
3/5 | 64800 | 38880 | {3, 12} | {11} | 285120 |
2/3 | 64800 | 43200 | {3, 13} | {10} | 216000 |
3/4 | 64800 | 48600 | {3, 12} | {14} | 226800 |
4/5 | 64800 | 51840 | {3, 11} | {18} | 233280 |
5/6 | 64800 | 54000 | {3, 13} | {22} | 237600 |
8/9 | 64800 | 57600 | {3, 4} | {27} | 194400 |
9/10 | 64800 | 58320 | {3, 4} | {30} | 194400 |