Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design

EURASIP Journal on Wireless Communications and Networking

Table 6 Comparing state-of-the-art synthesis results

	[5]	[6]	[7]	[15]	[16]	[31]	This^a	This^b	This^c
Technology (nm)	130	90	65	90/65	90	90	90	90	65
Freq. op. (MHz)	270	300	400	270	320	300	100/200	200	400
Power (mW)	-	-	-	477/-	-	-	85	-	-
Area (mm²)	22.7	4.1	3.9	13.1/6.0	9.6	12.4	6.2	-	3.2
Throughput (Mbps)	255	90	24-786	180	181-998	520	90	90	90
Max. number of iter.	30	30	15-50	-	15	25	7-16	14-32	28-64

ASIC synthesis results for state-of-the-art architectures in the literature
^a Synthesis results for the proposed optimized architecture with 45 FUs and a circuit clock frequency f_op = 100 MHz
^b Synthesis results for the proposed optimized architecture with 45 FUs and f_op = 200 MHz
^c Estimated synthesis results for the proposed optimized architecture with 45 FUs, scaled for a 65 nm process design with the same parameters as [7] (i.e., f_op = 400 MHz)