Table 3 FPGA resource utilization of each processing block

Virtex-II V2000

TX FIFO

64/10,752

93/21,504

2/56

0/56

80 MHz

RX FIFO

88/10,752

119/21,504

4/56

0/56

80 MHz

FEC TX

511/10,752

827/21,504

4/56

0/56

80 MHz (12.47 ns)

Symbol mapper

72/10,752

41/21,504

0/56

0/136

80 MHz

Soft decisor

1,500/10,752

2,597/21,504

1/56

2/56

80 MHz

FEC RX

2,260/10,752

3,591/21,504

6/56

0/56

80 MHz

Virtex-4 SX35

Synchronization (MS)

9,110/15,360

16,806/30,720

39/192

42/192

80 MHz

Frame control (BS)

496/15,360

1,002/30,720

25/192

0/192

80 MHz

DUC 10 MHz

2,455/15,360

3,447/30,720

16/192

26/192

160 MHz

DUC 8.75 MHz

1,305/15,360

1,784/30,720

10/192

13/192

160 MHz

DUC 3.5 MHz

1,266/15,360

1,769/30,720

10/192

11/192

160 MHz

DDC 10 MHz

4,567/15,360

6,901/30,720

12/192

44/192

160 MHz (12.10 ns)

DDC 8.75 MHz

2,466/15,360

3,904/30,720

10/192

15/192

160 MHz (12.10 ns)

DDC 3.5 MHz

2,947/15,360

4,918/30,720

11/192

13/192

160 MHz (12.10 ns)

Virtex-4 SX55

TX FIFO

182/24,576

305/49,152

15/320

0/512

100 MHz

RX FIFO

182/24,576

305/49,152

15/320

0/512

100 MHz

FFT

7,184/24,576

9,129/49,152

19/320

57/512

100 MHz (9.47 ns)

IFFT (BS)

7,551/24,576

9,799/49,152

66/320

59/512

100 MHz

IFFT (MS)

8,381/24,576

11,436/49,152

67/320

60/512

100 MHz (9.79 ns)