Table 4 Synthesis results
From: Dynamic voltage and frequency scaling scheme for an adaptive LDPC decoder using SNR estimation
Technology | Charted 0.18-μm CMOS |
|---|---|
LDPC total (in NAND2) | 316 K |
Check node (in NAND2) | 154 K |
Bit node (in NAND2) | 13 K |
AGU (in NAND2, with memory) | 82 K |
SNR estimator (in NAND2) | 31 K |
Parity check (in NAND2) | 1 K |
Tentative (in NAND2) | 1 K |
Critical Path Replicas (in NAND2) | 7 K |
Operating freq. (MHz) | 45 to 185 |
Voltage (V) | 0.9 to 1.8 |