Algorithm and hardware design of a 2D sorter-based K-best MIMO decoder

EURASIP Journal on Wireless Communications and Networking

Table 2 ASIC synthesis results of 4 ×4 K -best-based MIMO decoders

Design	[7], 2006	[6], 2006	[8], 2010	[9], 2012	[11], 2007	[12], 2010	[5], 2013	Proposed
Modulation	16-QAM	16-QAM	64-QAM	64-QAM	64-QAM	(4-64)QAM	64-QAM	(2-256)QAM
K value	5	5	5-64	10	64	N/A	10	21
Method	Real	Real	Real	Real	Complex	Complex	Complex	Complex
Process	0.35 µm	0.25 µm	65 nm	0.13 µm	0.13 µm	0.13 µm	0.13 µm	90 nm
Hard/soft decision	N/A	N/A	Hard	Hard	Soft	Soft	Hard	Soft
f_max (MHz)	100	132	158	282	270	198	417	590
Throughput	54	424	732-100	675	100	285-431	1,000	2,700
(Mbps)	210^a	1,178^a	529-72^a	975^a	140^a	411-623^a	1,444^a	2,700^a
Area (Kgate)	91	114	1,760	114	280	350	340	180
Power (mW)	626	N/A	165	135	94	57-74	1,700	56
NHE ^b (Mbps/Kgate)	2.33	10.3	0.3-0.04	8.5	0.52	1.18-1.79	4.26	15.2
Latency (µs)	2.4	0.4	N/A	0.6	N/A	N/A	0.36	0.07

^aNormalized throughput from S technology to 90 nm = (throughput at S) $\times \frac{S}{90}$ . ^bNormalized hardware efficiency (NHE) $= \frac{Normalized_throughput(Mbps)}{Area (Kgates)}$ .