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Table 2 FPGA resources comparison between HPW and existing schemes

From: Experimental analysis of PAPR reduction technique using hybrid peak windowing in LTE system

 

Flip flop

Look up table

Memory

DSP48

Logic

Shift register

(36 kbit)

(25 × 18)

CAF

2,012

328

54

8

21

PW

10,512

7,341

74

72

46

HPW

10,968

7,512

74

72

46