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Table 1 FPGA resource utilization table

From: A low-complexity peak cancellation scheme and its FPGA implementation for peak-to-average power ratio reduction

 

FFs

Slice LUTs

DSP48

RAM

   

(Multipliers)

 

Proposed

3,920

3,439

17

1

Conventional scheme1

3,354

3,117

15

4

(no iteration)

    

Conventional scheme1

6,785

6,341

30

8

(one iteration)

    

Conventional scheme2

5,749

5,383

171

0

Available in FPGA

607,200

303,600

2,800

1,030

  1. FF, flip flop; LUT, look-up table.