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Table 2 FPGA implementation of hardware architecture for multivariate signature generation

From: High-speed hardware architecture for implementations of multivariate signature generations on FPGAs

Signature scheme Message size Signature size L1 matrix L2 matrix Systems of linear equations Clock cycle Time frequency Executing time
enTTS(20,28) 20 B 28 B 20 × 20 28 × 28 9 × 9 90 100 MHz 0.9 μs