Fig. 9
From: Design and implementation of AD9361-based software radio receiver
The hardware implementation block diagram of channel equalization module. The hardware implementation block diagram of channel equalization module. SC-FDE symbols in the time domain are read from “buffer of RX frame sample” by the channel equalization module and sent to the FFT module to calculate the frequency domain values of SC-FDE symbols. Frequency domain values are read from “buffer of CSI” by the CSI_ACQ module, which can complete the integration of corresponding samples meanwhile. With the complex multiplication of the corresponding sample points completed by the FDE_CORE module, the frequency domain equalization is achieved