Table 1 Simulation parameters

Number of UEs

K=8

Number of subchannels

N=4

Total system bandwidth

B=2MHz

Reference channel power gain

μ₀=−50dB

Noise power density

N₀=−150dBm/Hz

Required CPU cycles for one bit

C=10³cycles/bit

CPU coefficient

γ_k=10⁻²⁸

Amplifier coefficient

ξ_k=3

Fixed circuit power

p_c,k=50mW

Maximum local CPU frequency

\(f_{k}^{\max } = 0.5 \times 10^{9} \mathrm {cycles/s}\)

Minimum required computation bits

\(R_{k}^{\min } = 10^{4}\text {bits}\)

Stop tolerances for Algorithm 1

ε₁=ε₂=10⁻³