Fig. 5
From: FPGA-embedded Linearized Bregman Iteration algorithm for trend break detection
Estimate of total number of clock cycles necessary for the algorithm to elapse considering the presented architecture. a Dependence with respect to the number of available parallel BRAMs for a fixed number of 10,000 data points and 650 iterations per data point. The gray-shaded areas highlight the transition between powers of 2, which manifests as sharp increases in the calculated value of C. b Dependence with respect to the number of data points for a fixed number of available BRAMs and 650 iterations per data point. The highlighted curve corresponds to 2000 BRAMs, which is the maximum available for the largest target FPGA studied here