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Table 2 Target FPGAs’ synthesis and timing results. Processing times calculated for N=10,000 and with L=6.5×106

From: FPGA-embedded Linearized Bregman Iteration algorithm for trend break detection

  Stratix V: 5SGSMD5K2F40C2 Cyclone V: 5CSXFC6D6F31C6
BRAMs ALMs Registers Memory [bits] Max. Clk. Proc. ALMs Registers Memory [bits] Max. Clk. Proc.
  out of 172, 600   out of 41, 246, 720 Freq. [MHz] time [s] out of 41, 910   out of 5, 662, 720 Freq. [MHz] time [s]
1024 135,571 (79%) 88,938 20,971,520 (51%) 109.9 1.91 1 1 1 1 1
512 68,135 (39%) 45,595 10,485,760 (25%) 166.97 1.78 1 1 1 1 1
256 36,098 (21%) 25,147 5,242,880 (13%) 173.28 2.78 36,548 (87%) 24,741 2,621,440 (46%) 81.13 5.94
128 19,196 (11%) 13,839 2,621,440 (6%) 182.12 4.70 20,178 (48%) 13,475 1,310,720 (23%) 95.37 8.98
16 4982 (3%) 4012 327,680 (< 1%) 182.35 33.83 5000 (12%) 3928 163,840 (3%) 92.94 66.37
4 3435 (2%) 2925 81,920 (< 1%) 187.86 130.08 3427 (8%) 2929 40,960 (< 1%) 91.73 266.40
  1. 1Design too large to fit into device