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Table 1 Implementation results of the example codes on a Xilinx Virtex-7 FPGA

From: Reduced-complexity decoding implementation of QC-LDPC codes with modified shuffling

Code Attributes LD, shuffled LD, non-shuffled
IEEE 802.15.3c
(672,336)
Clk freq. [MHz]
On-chip power [W]
Area (# LUTs)
209
0.840
15299
169
6.693
262122
IEEE 802.15.3c
(672,504)
Clk freq. [MHz]
On-chip power [W]
Area (# LUTs)
175
0.710
16007
144
5.461
218612
IEEE 802.15.3c
(672,425)
Clk freq. [MHz]
On-chip power [W]
Area (# LUTs)
200
0.900
14779
185
4.786
185478
IEEE 802.16.e
(2304,1152)
Clk freq. [MHz]
On-chip power [W]
Area (# LUTs)
114
2.640
185478