Table 3 Receiver system complexity analysis (for one information bit)
Unit | DCSK | CDSK | HE-DCSK | TR-DCSK | SR-PI-DCSK |
|---|---|---|---|---|---|
Multipliers | 1 | 1 | 1 | 0 | M/n |
Delay | 1 | 1 | 1 | 1 | L/n |
Demodulator | 1 | 1 | 1 | 1 | M/n |
DMU \(^{\mathrm {a}}\) | 0 | 0 | 0 | 1 | 1/n |
Unit | DCSK | CDSK | HE-DCSK | TR-DCSK | SR-PI-DCSK |
|---|---|---|---|---|---|
Multipliers | 1 | 1 | 1 | 0 | M/n |
Delay | 1 | 1 | 1 | 1 | L/n |
Demodulator | 1 | 1 | 1 | 1 | M/n |
DMU \(^{\mathrm {a}}\) | 0 | 0 | 0 | 1 | 1/n |