From: Beyond 100 Gbit/s Pipeline Decoders for Spatially Coupled LDPC Codes
Code (c, b, L) | (640,512,80) | |||||
---|---|---|---|---|---|---|
Architecture | Layered | Compact | Compact (2) | |||
Processing | Row | Column | Row | Column | Row | Column |
#Processors | 4 | 5 | 6 | 7 | 9 | 9 |
Comp. Compl. | 10240\(^{a}\) | 14080\(^{b}\) | 23040\(^{c}\) | 19712\(^{b}\) | 34560\(^{c}\) | 25344\(^{b}\) |
#Pipeline Stages | 10 | 13 | 8 | 10 | 20 | 21 |
Frequency [MHz] | 438 | 549 | 351 | 525 | 500 | 693 |
Core Area [mm\(^{2}\)] | 1.02 | 1.04 | 2.11 | 1.33 | 2.69 | 1.68 |
Utilization [%] | 82 | 76 | 77 | 77 | 80 | 77 |
Power Total [W] | 2.38 | 2.42 | 5.13 | 3.16 | 4.42 | 3.78 |
Power Density [W/mm\(^{2}\)] | 2.35 | 2.33 | 2.43 | 2.37 | 1.65 | 2.24 |
Throughput [Gbps] | 280 | 351 | 224 | 336 | 320 | 443 |
Latency [ns] | 22.8 | 23.7 | 22.8 | 19.0 | 40.0 | 30.3 |
Area Eff. [Gb/s/mm\(^{2}\)] | 276 | 338 | 107 | 252 | 119 | 263 |
Energy Eff. [pJ/bit] | 8.5 | 6.9 | 22.8 | 9.4 | 13.8 | 8.5 |
Energy Eff. per proc. [pJ/bit] | 2.1 | 1.4 | 3.8 | 1.3 | 1.5 | 0.94 |