Charge-Domain Signal Processing of Direct RF Sampling Mixer with Discrete-Time Filters in Bluetooth and GSM Receivers

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INTRODUCTION
The continuous technology innovation in CMOS forces to integrate more circuits resulting in lower solution price while offering more features [1].Designing a radio for the wireless and cellular standards with large digital circuitry, such as digital baseband (DBB), application processor, and memory on the same chip becomes a challenging task due to the coupling of the digital spurious noise through silicon substrate, interconnect, and package [2].While high level of integration impedes achieving a low noise figure, low supply voltage makes linearity hard to achieve.
Recently, we have demonstrated a highly integrated system-on-chip (SoC) in the discrete-time Bluetooth receiver.The receiver architecture [3][4][5][6] uses direct RF sampling in the receiver front-end path.In the past, only subsampling mixer receiver architectures have been demonstrated: they operate at lower IF frequencies [7,8] and suffer from noise folding and exhibit susceptibility to clock jitter.In this architecture, discrete-time analog signal processing is used to sample the RF input signal as it is down-converted, down-sampled, filtered, and converted from analog to digital with a discretetime ΣΔ ADC.This method achieves great selectivity right at the mixer level.The selectivity is digitally controlled by the LO clock frequency and capacitance ratio, both of which are extremely precise in deep-submicron CMOS processes.The discrete-time filtering at each signal processing stage is followed by successive decimation.The main philosophy in architecting the receive path is to provide all the filtering required by the standard as early as possible using a structure that is quite amenable to migration to the more advanced deep-submicron processes.This approach significantly relaxes the design requirements for the following baseband amplifiers.
In this paper, we also present a 90-nm CMOS realization of a GSM receiver [9][10][11] RF front end incorporating the discrete-time signal processing.The RF front end provides an embedded variable gain amplifier (VGA) function that is digitally configurable and offers fine gain control.The switched capacitor filter (SCF) implements a highly-linear second-order lowpass filter.The input S 11 is constant over the desired frequency range while achieving 1.8 dB noise figure (NF) in the highest gain setting of 40 dB where the RF front-end circuits consume only 15.3 mA.The gain can be configured with an automatic-gain-control algorithm in the receiver to select an optimal setting with a trade-off between noise figure and linearity and to compensate for process and temperature variations.The objective is to realize a receiver front-end circuit with adjustable lowpass filters that is small in size while enabling the software-defined radio (SDR) of the future.The organization of this paper is as follows.Section 2 presents discrete-time signal processing of the RF front-end mixer with an emphasis on Bluetooth examples.Section 3 describes a specific implementation of the described techniques and concepts in a GSM front-end radio.Silicon realization of the Bluetooth and GSM radios is presented in Section 4. Performance of the GSM front-end receiver is shown in Section 6.

Direct sampling mixer
The basic idea of the current-mode direct sampling mixer [3,4] is illustrated in Figure 1(a).The low-noise transconductance amplifier (LNTA) converts the received RF voltage v RF into i RF in current domain through the transconductance gain g m .The current i RF gets switched by the half-cycle of the local oscillator (LO) and integrated into the sampling capacitor C s .Since it is difficult to switch the current at RF rate, it could be merely redirected to an identical sampler that is operating on the opposite half-cycle of the LO clock, as shown in Figure 1(b) for a pseudodifferential configuration.
If the LO oscillating at f 0 frequency is synchronous and in phase with the sinusoidal RF waveform, the voltage gain of a single RF half-cycle is Temporal MA operation at RF rate with cyclic charge readout.
and the accumulated charge on the sampling capacitor is In the above equations, the 1/π factor is contributed by the half-cycle sinusoidal integration.As an example, if g m = 30 mS, C s = 15.925pF, and f 0 = 2.4 GHz, then G v,RF = 0.25.

Temporal moving average
Continuously accumulating the charge as shown in Figure 1 is not very practical if it cannot be read out.In addition, a mechanism to prevent the charge overflow is needed.Both of these operations are accomplished by fixing the integration window length followed by charge readout phase that will also discharge the sampling capacitor such that the next period of integration would start from the same zero condition.The RF sampling and readout operations are cyclically rotated on both C s capacitors as shown in Figure 2. When LO A rectifies N RF cycles that are being integrated on the first sampling capacitor, LO B is off and the second sampling capacitor charge is being read out.On the following N RF cycles the operation is reversed.This way, the charge integration and readout occur at the same time and no RF cycles are missed.
The sampling capacitor integrates the half-rectified RF current over N cycles.The charge accumulated on the sampling capacitor and the resulting voltage (V = Q/C s ) increases with the integration window, thus giving rise to a discrete signal processing gain of N.
The temporal integration of N half-rectified RF samples performs a finite-impulse response (FIR) operation with N all-one coefficients, also known as moving-average (MA), according to the equation where u i is the ith RF sample of the input charge sample, w i is the accumulated charge.Since the charge accumulation is done on the same capacitor, this formula could also be used in the voltage domain.Its frequency response is a sinc function and is shown in Figure 3 for N = 8 (solid line) and N = 7, 9 (dotted lines) with sampling rate f 0 = 2.4 GHz.It should be noted that this filtering is done on the same capacitor in time domain resulting in a most faithful reproduction of the transfer function.
Due to the fact that the MA output is being read out at the lower rate of N RF clock cycles, there is an additional aliasing with foldover frequency at f 0 /2N and located halfway to the first notch.Consequently, the frequency response of MA = 7 with decimation of 7 exhibits less aliasing and features wider notches than MA = 8 or MA = 9 with decimation of 8 or 9, respectively.
It should be emphasized that the voltage G v and charge G q signal processing gains of the temporal moving average (TMA) (followed by decimation) are merely due to the sampling time interval expansion of this discrete-time system (the sampling rate of the input is at the RF frequency): G v,tma = G q,tma = N.
In the following analysis, the RF half-cycle integration voltage gain of g m /πC s f 0 is tracked separately.Since this gain depends on the absolute physical parameters of usually low tolerance (g m value of the preceding LNTA stage and the total integrating capacitance of the sampling mixer), it is advantageous to keep it decoupled from the discrete signal processing gain of the MTDSM.

High-rate IIR filtering
Figure 2 is now modified to include recursive operation that gives rise to the IIR filtering capability, which is generally considered stronger than that of FIR.
A "history" sampling capacitor C H is added in Figure 4.The integration operation is continually performed on the "history" capacitor C H = a 1 C s and one of the two rotating "charge-and-readout" capacitors C R = (1 − a 1 )C s such that the total RF integrating capacitance, as seen by the LNTA, is always C H + C R = C s .When one of the C R capacitors is being used for readout, the other is being used for RF integration.
The IIR filtering capability comes into play in the following way.The RF current is being integrated over N RF cycles, as described before.This time, the charge is being shared on both C H and C R capacitors proportionately to their capacitance values.At the end of the accumulation cycle, the active C R capacitor, that stores (1 − a 1 ) of the total charge, stops further accumulating in preparation for charge readout.The other rotating capacitor joins the C H capacitor in the RF sampling process and, at the same time, obtains (1 − a 1 )/(a 1 + (1 − a 1 )) = 1 − a 1 of the total remaining charge in the "history" capacitor, provided it has no initial charge at the time of commutation.Thus the system retains a 1 portion of the total system charge of the previous cycle.
If the input charge accumulated over the most recent N RF samples is w j , then the charge s j stored in the system at sampling time j, where i = N • j (as stated earlier, i is the RF cycle index) could be described as a single-pole recursive IIR equation: The output charge x j is (1 − a 1 ) of the system charge in the most recent cycle.This discrete-time IIR filter operates at f 0 /N sampling rate and introduces a single pole with the frequency attenuation of 20 dB/dec.The equivalent pole location in the continuous-time domain for f c1 f 0 /N is Since there is no sampling time expansion for the IIR operation, the discrete signal processing charge gain is one.In other words, due to the charge conservation principle, the input charge per sample interval is on average the same as the output charge.For the voltage gain, however, there is an impedance transformation of C input = C s and C output = (1 − a 1 )C s , thus resulting in a gain: As an example, the IIR filtering with a single coefficient of a 1 = 0.9686, placing the pole at

Additional spatial MA filtering zeros
For practical reasons, it is difficult to read out the x j output charge of Figure 4 at f 0 /N = 300 MHz rate.The output charge readout time is extended M = 4 times by adding redundancy of four to each of the two original C R capacitors as shown in Figure 5.The input charge is cyclically integrated within the group of four C R capacitors.Adding the redundant capacitors gives rise to an additional antialiasing filtering just before the second decimation of M. This could also be considered as equivalent to adding additional M − 1 zeros to the IIR transfer function in (4).After the first bank of four capacitors gets charged (S A1 − S A4 in Figure 5), the second bank (S B1 − S B4 ) is in the process of being charged and the charge on first bank of capacitors are summed and read out (R A ). Physically connecting together the four capacitors performs an FIR filtering described as the spatial moving average of M = 4: where y k is the output charge and sampling time index j = M • k.R A and R B in Figure 5 are the readout/reset cycles during which the output charge on the four nonsampling capacitors is transferred out and the remnant charge is reset before the capacitors are put back into the sampling operation.
It should be noted that after the reset phase, but before the sampling phase, the capacitors are unobtrusively precharged [5] in order to implement a dc-offset cancellation or to accomplish a feedback summation for the ΣΔ loop operation.Since the charge of four capacitors is added, there is a charge gain of M = 4 and a voltage gain of 1. Again, as explained before, the charge gain is due to the sampling interval expansion: G q,sma = M and G v,sma = 1.
Figure 6 shows frequency response of the temporal moving average with a decimation of 8 (G v = 18.06 dB), the IIR filter operating at RF/8 rate (G v = 30.06dB), and the spatial moving average filter operating at RF/32 rate (G v = 0 dB) with a decimation of 4. The solid line is the composite transfer function with the dc gain of G v = 48.12dB.The first decimation of N = 8 reveals itself as aliasing.It should be noted that it is possible to avoid aliasing of a very strong interferer into the critical IF band by simply changing the decimation ratio N.This brings out advantages of integrating RF/analog with digital circuitry by opening new avenues of novel signal processing solutions not possible before.

Lower-rate IIR filtering
The voltage stored on the rotating capacitors cannot be readily presented to the MTDSM block output without an active buffer that would isolate the high impedance of the mixer from the required low driving impedance of the output.
Figure 7 shows the mechanism to realize the second, lowerrate, IIR filtering through passive charge sharing.The active element, the operational amplifier, does not actually take part in the IIR filtering process.It is merely used to sense voltage of the buffer feedback capacitor C B and present it to the output with a low driving impedance.operational amplifier, the opposite (180 degree apart) processing path.
The charge y k accumulated on the M = 4 rotating capacitors is being shared during the dumping phase with the buffer capacitor C B .At the end of the dumping phase, the M • C R capacitors get disconnected from the second IIR filter and their charge reset before they could be reengaged in the MTDSM operation of Figure 5.This charge loss mechanism gives rise to IIR filtering.If the input charge is y k , then the charge z k stored in the buffer capacitor C B at sampling time k is Equation ( 10) describes a single-pole IIR filter with coefficient a 2 and input y k scaled by a 2 , where a 2 corresponds to the storage-to-total capacitance ratio C B /(C B + MC R ).Conversely, due to the linearity property, it could also be thought of as an IIR filter with input y k and output scaled by a 2 .This discrete-time IIR filter operates at f 0 /NM sampling rate and introduces a single pole with the frequency transfer function attenuation of 20 dB/dec.The equivalent pole location in the continuous-time domain for f c2 f 0 /(NM) is The actual MTDSM output is the voltage sensed on the buffer feedback capacitor z k /C B .The previously used charge stream model cannot be directly applied here because the "output" charge z k is not the one that leaves the system.
The charge "lost" or reflected back into the M • C R capacitor for subsequent reset is (1 − a 2 )(z k−1 + y k ).Due to charge conservation principle, the time-averaged values of charge input, y k , and charge leaked out, (1 − a 2 )(z k−1 + y k ), should be equal.As stated before, the leak-out charge is not the output from the signal processing standpoint.It should be noted that the amplifier does not contribute to the net charge change of the system and, consequently, the only path of the charge loss is through the same M •C R capacitors being reset after the dumping phase.
The output charge z k stops at the IIR-2 stage and does not further propagate, therefore it is of less importance for signal processing analysis.The charge discrete signal processing gain of the second IIR stage is The input/output impedance transformation is MC R /C B .Consequently, the voltage gain of IIR-2 is unity:

Cascaded MTDSM filtering
The cascaded discrete signal processing gain equations of the MTDSM mixer are Including the RF half-cycle integration (1) and ( 2), the total single-ended gain is Note the similarity between (17) and (1).In both cases, the term R sc = 1/ f s C s is an equivalent resistance of a switched capacitor C s sampling at rate f s .For example, if f s = 300 MHz and C R = 0.5 pF, then the equivalent resistance is R sc = 6.7 kΩ.Since the MTDSM output is differential, the gain values in the above equations are actually doubled.The dc-frequency gain G v,tot in (17) requires further elaboration.The gain depends only on the g m of the LNTA stage, rotating capacitor value, and the rotation frequency.Amazingly, it does not depend on the other capacitor values, which contribute only to the filtering transfer function at higher frequencies.

Near-frequency interferer attenuation
Most of the lower-frequency filtering could be realistically done only with the first and second IIR filters.The two FIR filters do not have appreciable filtering capability at low frequencies and are mainly used for antialiasing.
It should be noted that the best filtering could be accomplished by making 3-dB corner frequencies of both IIR filters the same and placing them as close to the higher end of signal band as possible: This gives the following constraint:

Signal processing example
Figure 8 shows the block diagram from the signal processing standpoint for our specific implementation of f 0 = 2.4 GHz, N = 8, M = 4.The following equations describe the timedomain signal processing: (3) for w i , (4) and ( 5) for x j , (9) for y k , and (10) for z k .The first aliasing frequency (at f 0 /N = 300 MHz) is partially protected by the first notch of the temporal MA = 8 filter.However, for higher-order aliasing and overall system robustness, it has to be protected with a truly continuous-time filter, such as an antenna filter.A typical low-cost Bluetoothband duplexer can attenuate up to 40 dB at 300 MHz offset.
For the above system with an aggressive cut-off frequency of f c1 = f c2 = 1.5 MHz, using C R = 0.5 pF will result in a dc-frequency voltage gain of 63.66 or 36 dB (17) and the required capacitance is C H = 15.425pF (7) and C B = 13.925pF (12).The z-domain coefficients of the IIR filters are a 1 = 0.9686 and a 2 = 0.8744.The dc-frequency gains are G v,iir1 = 31.85and G v,iir2 = 1.The transfer function of these IIR filters is shown in Figure 9.The spatial MA = 4, which follows IIR-1, does not appreciably contribute to filtering at lower frequencies but serves as an antialiasing filter for the lower-rate IIR-2.Since the 3-dB point of IIR-2 is slightly corrupted by the discrete-time approximation, the composite attenuation at the cut-off frequencies f c1 = f c2 = 1.5 MHz is about 5.5 dB.The attenuation drops to 13 dB at 3 MHz.
Within the 1 MHz band of interest, there is a 3-dB signal attenuation.For the most optimal detector operation, this in-band filtering should be taken into consideration in the matched-filter design.Figure 10 shows the phase response of the above structure versus the ideal constant group delay.

MTDSM feedback path
The MTDSM feedback correction could be unobtrusively injected into either group of the four rotating capacitors of Figure 5 when they are not in the active sampling state.This way, the main signal path is not perturbed.The feedback correction is accomplished through charge injection/equalization between the "feedback capacitor" C F and the rotating capacitors C R in the MTDSM structure by shorting all of them together after the C R group of capacitors gets reset, but before they are put back to the sampling system.The feedback charge accumulation structure is shown in Figure 11.Each feedback capacitor C F is associated with one of the two rotating capacitors of group "A" and "B."The two groups commutate the charging process.
Voltage on the feedback capacitor can be calculated as follows.Charging the feedback capacitor C F with the current i fbck for the duration of T will result in incremental accumulation of ΔQ in = i fbck • T charge.This charge gets  added to the total charge Q F (k) of the feedback capacitor at the kth time instance: During the charge distribution moment, the feedback capacitor gets connected with the previously reset group of rotating capacitors M • C R .The charge depleted from C F is dependent on the relative capacitor values: The charge transferred to the rotating capacitors is proportional to the total accumulated charge Q F or voltage on the feedback capacitor V F = Q F /C F .At first, the accumulated charge is small, so the outgoing charge is small.Since the incoming charge is constant, the Q F charge will continue accumulating until the net charge intake becomes zero.Equilibrium is reached when ΔQ in (k) = ΔQ out (k): Transformation of the above gives the equilibrium voltage: The ΔQ out,eq charge transfer into the rotating capacitors at equilibrium will create voltage on the bank of rotating capacitors: As shown in Section 2.5, the voltage transfer function from the rotating capacitors to the history capacitor is unity.Therefore, the bias voltage developed on C H is

A GSM RECEIVER FRONT-END ARCHITECTURE
The receiver front end is shown in Figure 12 and consists of an LNA followed by two transconductance amplifiers (TAs) and two passive mixers.The RF input signal is amplified by the LNA and splits into I/Q paths where it is further amplified in the TA.It is then down-converted to a low intermediate frequency (IF) that is fully programmable (but defaults to 100 kHz) by the following mixers driven by an integrated local oscillator (LO).The IF signal is sampled and lowpass-filtered by passing through the switched-capacitor filter (SCF).The LO signals are generated using an all-digital PLL (ADPLL) [12] that incorporates a digitally controlled oscillator (DCO).The digital control unit (DCU) provides all the clocks for the SCF operation.
Although the front-end circuit requires two TAs, two mixers, and quadrature LO signals, the receiver has an excellent sensitivity and good linearity at a low supply voltage (V DD ) of 1.4 V thus offering excellent performance that satisfies the GSM requirements.The power is supplied by an integrated low-drop-out (LDO) regulator.

Low-noise amplifier
A differential LNA is implemented to improve noise figure which could be degraded by substrate coupling originating from DBB since the impact of the switching noise of more than a million digital gates on the same silicon die could not have been known precisely.Figure 13 shows a simplified schematic diagram of the LNA.A variable gain feature with seven digitally configurable steps is implemented.In the high-gain mode, four voltage gains are realized with a 2-dB step between 21 dB and 29 dB.In the low-gain mode, there are three gain steps with a 2-dB step between 3 dB and 9 dB.As shown in Figure 13, the multiple cascode stages are connected in parallel with one source degeneration inductor and one inductive load.Each stage has digital configurability.The top transistors of the cascode stage used for bypassing gain contribution are shunted to V DD .Since the bottom transistors of the cascode stage operate in all gain settings, the input impedance is constant to the first order over gain selections, which is critical for constant input power and noise matching.Inductive source degeneration using package bond wires is implemented to improve linearity.The LNA load is an on-chip spiral inductor using multiple metal layers with metal width = 5.9 μm, metal space = 2 μm, inner diameter = 81.9μm, and 10 turns.This inductor is drawn as a center-tap configuration for better matching between the differential branches and achieving a higher quality factor (Q).As shown in Figure 14, the inductance is 8.9 nH and Q is > 4 at 900 MHz, where Q is defined as |imag(y11)/real(y11)|.To reduce the substrate effect, all doping under the inductor is blocked to preserve a higher resistivity.The inductor is tuned with the capacitance at the LNA load which comprises tuning capacitors together with parasitics.The tuning capacitor is realized using metal-insulatormetal (MIM) capacitors and switches.Two capacitors are connected differentially with a switch and two pull-down transistors to keep both source/drain voltages of the switch low and Q of the capacitor bank high.The achieved effective Q is 100 at 900 MHz.When the switch is turned off to be in a low capacitance value, the parasitic capacitance of the MIM capacitors and transistors still has an effective Q of about 100.Compared to MOS capacitor, MIM capacitor provides a much better trade-off between Q and C ON /C OFF ratio.In this design, a C ON /C OFF ratio of larger than 4 was achieved while Q is still greater than 100.The selectable capacitance ranges 2.5 pF in total because in this process, MIM capacitance can vary up to +/ − 20% from its nominal value.With this design, all GSM bands can be fully covered.
The differential LNA draws 7.3 mA.The LNA input is protected against ESD by one reverse-biased diode to V DD and three forward-biased diodes in series to V SS .ESD structures at LNA input are aimed to protect larger than 2 kV human body model (HBM).The LNA bond pad is shielded with lower metal-1 layer to eliminate the substrate coupling while minimizing parasitic capacitance which is about 100 fF.

TA and mixer
Figure 15 shows a simplified TA and mixer schematic diagram.A highly efficient push-pull amplifier is chosen for the TA because of its low noise and good linearity characteristics.The variable gain feature is implemented in the TA with a 3-bit control.A feedback amplifier is used to set the dc bias voltage of the TA output node to V REF which is set to half of V DD so as to provide maximum signal swing.Resistors in Figure 15 are large enough to prevent significant RF signal loading.The differential TA draws 4 mA in the maximum gain mode.
A double-balanced switching mixer is connected to the TA output via ac-coupling capacitors so that the dc voltage at the TA output is isolated from the mixer.This topology has an excellent feature of reduced 1/f noise because there is no dc current flowing through making it suitable for directconversion or near-zero IF receivers.By adding a capacitive load (C H , history capacitor) to the mixer output, lowpass filtering can be obtained to reduce large interferers.In this mixer, two switches are toggled by one of the complementary LO signals (LO+, LO−) from a digitally controlled oscillator (DCO).Since the mixer is connected to the switched capacitor filter (SCF), its loading effect can be represented as R load which is about 4.5 kΩ.

SCF
The schematic diagram of the switched capacitor filter block (SCF) is shown in Figure 16.The switches are controlled by the digital control unit (DCU) that generates the timing waveforms shown in Figure 17.For one LO cycle, the RF signal of the mixer output is integrated into a history capacitor (C H ) and a rotating capacitor (C R1 ).Since the four rotating capacitors sequentially connect to C H in a fixed order, the charge transfer via C R1 is a direct sampling of IF signal.It is also clear that a charge loss on C H through C R1 creates the loading (R load ) to the mixer output.For two LO cycles, two rotating capacitors in the first bank sample the IF signal on C H while the rotating capacitors in the second bank and C B1 share charge.Because of the half sampling rate from the mixer output to C B1 , the decimation operation creates a sinc function that has notches at the foldover frequencies, NLO/2, where N is a positive integer.Transconductance (g m ) of TA, C H and the loading (R load ) of SCF create the first IIR filtering response of g m -C antialiasing lowpass filtering prior to the main sinc filter.However, the TA sees a periodic constant load at its output.
After the two C R1 capacitors in one bank are disconnected from C H , these carry the charge of past 2 IF samples created by the charge sharing between two C R1 and C H . Next, the two C R1 capacitors share charge with the buffer capacitor C B1 and a second rotating capacitor, C R2 .The overall effect is to create a second IIR filtering stage in which 2C R1 delivers input, C B1 holds the memory, and C R2 captures a glimpse of the output of the second IIR filter stage.This charge is subsequently shared with a second buffer capacitor, C B2 , resulting in the third IIR filter stage.While charge samples are passed on from the C H to C B2 through a series of charge combination, splitting and recombination operations, the IF information at mixer output are always kept on C H together with two C R1 capacitors from one bank.The three IIR filters have corner frequencies that are given by respective ratios of rotating capacitors (C R1 , C R2 ) to fixed capacitors (C H , C B1 , C B2 ) and may be readjusted by changing the size of the capacitors.The capacitor ratios in the SCF are programmable which allows the filter corner frequency to be adjustable over a wide range, thereby allowing its use in a multistandard environment.
After the charge sharing of C R2 with C B2 , C R2 is reset (RA, RB) and precharged (PA, PB) by the 1-bit feedback circuit (FB-DAC) provided by a sigma-delta modulator that connects the output of a low-noise feedback voltage reference to C R2 .Zero DAC code produces approximately 50% duty cycle at FM and FP clocks which brings the common mode voltage of the SCF exactly at half of V REF .In the presence of a dc offset, the duty cycle is changed with sigma-delta noise shaping to cancel the offset voltage.

DCO
A DCO circuit schematic is shown in Figure 18 [12].L1A and L1B are two halves of a center-tap inductor.Because of the shortcoming of this 90-nm digital CMOS Cu process which has thin metal interconnects, it is difficult to design an inductor with even a moderate Q.To enhance the Q of the inductor, an Al layer is patterned and connected in parallel with the Cu windings.M3-5 plus the Al layer were used to form L1 while only M3-5 layers were used for L0.The total Cu and Al thickness are only 0.75 μm and 1.0 μm, respectively.The simulated single-ended Q using an imag(y11)/real(y11) definition is 3.6 and 6.7 at 0.9 and 3.6 GHz, respectively.The differential phase stability Q is 3.6 and 10.2 at 0.9 and 3.6 GHz, respectively [13].
The varactor is implemented using an npoly-nwell MOSCAP structure.Extrapolating from measurement data, the Cmax/Cmin ratio is > 3 within the ranges of desired gate length Lg and gate width Wg per finger.The resulting total tolerable fixed parasitic capacitance is 720 fF.MOSCAP was chosen because the gate oxide thickness (tox) is one of the best controlled parameters in this CMOS process, whose corner variation is within +/ − 2.5%.The four different phases of LO driving the I-and Q-mixers in Figure 15 are generated from the DCO frequency which oscillates at 4ω 0 , where ω 0 is in the GSM band frequencies.A fully digital circuit (ADPLL) is built around the DCO to adjust its phase and frequency deviations in a negative feedback manner.

SILICON REALIZATION
The presented techniques have been realized in silicon.Figure 19 shows two chip micrographs representing the first and second generation of digital RF processor (DRP), respectively: (1) commercial 10 mm 2 single-chip Bluetooth radio in 130 nm CMOS, and (2) a fully functional preproduction version of the single-chip GSM radio in 90-nm CMOS.The GSM chip consists of two independent pairs of transmitters and receivers to study various on-die coupling mechanisms, which are especially important in full-duplex WCDMA operations with RX and TX diversity.The 90-nm process features the following parameters that characterize the process: 0.27 μm minimum metal pitch, five levels of copper metal, 1.2 V nominal transistor voltage, 2.6 nm gate oxide thickness, logic gate density of 250 kgates/mm 2 , SRAM cell density of 1.0 Mb/mm 2 .The measured RX sensitivity of −82 dBm for Bluetooth and −110 dBm for GSM, versus the respective specifications of −70 dBm and −102 dBm, is quite competitive with conventional solutions.The overall GSM RX noise figure is only 2 dB.

GSM RX FRONT-END PERFORMANCE
The LNA input is matched using an external inductor and a capacitor with a balun for impedance ratio of 50 to 100 Ω.The measured LNA input matching with S 11 is < −10 dB over the whole GSM band.When the curves of S 11 versus multiple LNA gains are compared, largest variation is less than 1 dB. Figure 20 displays the front-end voltage gains versus different LNA and TA gain settings.The front-end gains can be configured with an automatic-gain-control (AGC) function to select an optimal gain setting trading off noise figure for linearity.This circuit adds 32.5 dB dynamic range to the receiver.The LNA, two TAs, and mixers consume 15.3 mA from an internal LDO voltage of 1.4 V. Since this work has digitally configurable gain with a fine resolution, it is different from a conventional front-end approach that is typically built for two large steps.A major advantage of our approach is that  the circuit performance can be finely optimized by selecting the appropriate gain settings.Table 1 summarizes the measured performance when the front-end gain of 34 dB is selected with LNA gain setting number 6 (max −2 dB) and TA gain setting number 3.
Since the SCF is a highly-linear filter, little degradation in linearity has been measured.In Figure 21, two pairs of measured plots at SCF output show the lowpass filtering where the 3-dB frequencies are set to 150 kHz and 270 kHz.

CONCLUSION
We have presented an RF direct sampling technique that achieves great selectivity right at the mixer level.The dynamic range requirements of the following ADC are thus significantly relaxed.The selectivity is digitally controlled by the LO clock frequency and the capacitance ratio, both of which are extremely precise in digital deep-submicron CMOS processes.In order to validate the proposed technique, the multitap direct sampling mixer (MTDSM)-based front-end RX has been fabricated as part of commercial Bluetooth and GSM radios in digital deep-submicron CMOS processes.We have also presented implementation details of the GSM receiver front end realized in a 90-nm digital CMOS technology.It includes LNA, transconductance amplifier (TA), mixer for I  and Q channels with switched capacitor filter (SCF).While providing 35 digitally configurable gain steps ranging from 40 dB down to 7.5 dB, this fully integrated front-end circuit demonstrates a good noise figure of 1.8 dB at 40 dB maximum gain and +50 dBm IIP2 at 34 dB of gain, while a million of digital logic gates are simultaneously running on the same die.This paper demonstrates feasibility and attractiveness of employing the charge-domain RF signal processing within a larger system-on-chip (SoC) designs.

Figure 3 :
Figure 3: Transfer function of the temporal MA operation at RF rate.

Figure 5 :
Figure 5: IIR operation with additional FIR filtering.The readout and reset circuitry is not shown.

Figure 6 :
Figure 6: Transfer functions of the temporal MA filter and the IIR filter operating at RF/8 rate.The solid line is the composite transfer at the output of the spatial MA filter.

Figure 8 :
Figure 8: Discrete signal processing in the MTDSM.

Figure 9 :
Figure 9: Transfer functions of the IIR filters with two poles at 1.5 MHz (bottom zoomed).

Figure 10 :
Figure 10: Phase response of the IIR filters with two poles at 1.5 MHz.

Figure 11 :
Figure 11: Feedback into the rotating capacitors.

Figure 19 :
Figure 19: Die micrographs of radios employing two generations of DRP: (a) the commercial single-chip Bluetooth radio; (b) the preproduction version of the single-chip GSM radio.