OV-CDMA System: Concept and Implementation
© E. Inaty and R. Ayoubi. 2008
Received: 7 September 2007
Accepted: 25 January 2008
Published: 13 February 2008
A new method is proposed to achieve a multirate overlapped code division multiple access system (OV-CDMA) based on a novel code overlapping procedure. The signal-to-interference ratio (SIR) performance has been investigated for such system. A channel model that allows multirate overlapped transmission is presented based on which a closed form solution for the SIR has been derived. In addition, a simple yet very efficient block diagram of the transmitter and the receiver architecture has been proposed for such a system. Based on the proposed block diagram, the encoder-decoder has been implemented using an FPGA. Numerical results show that the newly proposed OV-CDMA scheme outperforms the classical variable processing gain fast frequency hopping CDMA (VPG-FFH-CDMA) for different system scenarios. Finally, real-time measurements have been successfully obtained using a hardware prototype utilizing the simple Xilinx Spartan IIE (XC2S200E) FPGA.
During the past few years, there has been a growing interest in the development of broadband wireless communication networks for multimedia applications. The communication services in such networks can be high- and low-speed data, video, and many others with different performance and traffic requirements [1–3].
Classical fast frequency hopping CDMA (FFH-CDMA) has been discussed in many works [4–6]. A multirate FFH-CDMA system using variable processing gain (PG) (VPG-FFH-CDMA) has been proposed in [3, 7, 8]. The intention was to guarantee the one-to-one correspondence between the PG and the source transmission rate. The drawback of this system is the drastic decrease in the transmitted signal power especially for higher rate users for which the PG becomes very small. The solution to this problem is the use of power control ; on the other hand, Kwong and Yang in [7, 8] considered the multilength frequency hopping codes. Using these codes, rate and QoS are now dynamically matched to users' needs. The cutoff rate of the system is still limited by the physical constraints of the codes.
In this work, the general problem we considered is how much we can increase the transmission rates of different classes of traffic beyond the nominal permitted rates. Our aim is to optimize performance to meet the quality of service (QoS) requirements given a fixed number of users in the network and a multimedia distribution. For an optimized family of codes, we will show that it is possible to increase a class bit rate beyond the nominal rate without decreasing the PG of the desired user or allowing any time delay between the data symbols. Our system achieves a multirate transmission by introducing an overlap between the transmitted symbols, hence the name overlapped code division multiple access system (OV-CDMA). In addition, we will consider the implementation of the OV-CDMA system . The control unit of the transmitter and the receiver has been accomplished using FPGA. A pipeline technique is used to achieve a high-computational efficiency. A prototype is built and tested. We have been able to achieve a transmission rate ranging from 0.1 to 20 Mbps. It is imperative to mention that the five-channel case implemented in this paper can be easily modified to higher number of channels. This is the main advantage of FPGA .
The paper is organized as follows. In Section 2, we present the OV-CDMA encoding/decoding technique. Section 3 derives the performance of the OV-CDMA system. Section 4 describes the OV-CDMA system implementation where the block diagrams of the transmitter and the receiver are presented and discussed. In addition, the hardware implementation using FPGA is discussed in Section 5. Section 6 contains the numerical results and the measurements. Finally, the conclusion is presented in Section 7.
2. OV-CDMA System Model
In this paper, we assume the following: (1) a chip and bit synchronous system and a discrete rate variation, (2) all users in the class-s, have the same bit overlap coefficient ; thus each class is characterized by , and (3) a unit transmission power for all the users.
2.1. Signal Structure
2.2. Decoder's Output
3. OV-CDMA Performance Evaluation
where is a random variable with a Rayleigh distribution assuming a Rayleigh fading channel. Thus the distribution of is exponential .
3.1. Effective Increase in the Number of Hits
3.2. Average SIR
where . In (20), we have been able to separate the interference power into the normal MAI power caused by active users when and the one caused by virtual users that overlap with the desired user's code when .
4. OV-CDMA System Implementation
Throughout this paper, and without loss of generality, the analysis is based on the five-channel example presented in Figure 1. The problem of designing a transmitter that performs the overlapping operation is simplified to find a way to transmit more that one frequency channels duringthe same chip period T c as shown in Figure 1.
4.1. OV-CDMA Transmitter Implementation
For example, during the first period T c , the transmitter should send channels , , and at the same time. Classical FFH-CDMA transmitters use what is widely known as frequency synthesizer to generate one carrier frequency at each T c seconds. It cannot generate multifrequency at the same time. For this reason, we propose a new architecture based on multifrequency generators and a switching operation that is performed by a central processing unit as revealed by Figure 4(a). The control unit will determine the switches which must be closed and the other which should be open. The result is summed and transmitted. This task can be easily accomplished using the desired user's code as shown in Figure 4(b). The above five-by-five matrix of binary data represents the digital control code that must be used by the control unit for the five-channel example shown in Figure 1. Note that during the first chip duration, the switches are controlled by the first row of the matrix such that , , and are closed, and and are open. This enables us to transmit simultaneously channels , , and . This matrix will be repeated every bit duration .
4.2. OV-CDMA Receiver Implementation
The receiver should first perform the decoding operation of the overlapped code then decide whether the transmitted bit is zero or one. The block diagram of the receiver is shown in Figure 5. It is composed of two major parts: the analog part and the digital part using FPGA. In the analog circuitry part, the incoming radio frequency signal is detected using the CDM2502 antenna. The incoming electric signal is subdivided into five channels with equal power. Then, for every channel, a bandpass filter (BPF) is used with a center frequency , which is one of the employed channels by the desired user. An energy detector (ED) is used to measure the energy of the filtered signal. An analog-to-digital converter (ADC) is utilized in order to convert the analog information from the ED into digital one so that it can be accepted by the FPGA logic.
It is imperative to mention that we will use the same code logic used in the encoder side. This code replica is used to dispread the received signal and to obtain the transmitted data stream. The outputs of the ADCs are held inside the registers then shifted to the right at every time period T c . After five consecutive cycles, a matrix is constructed. The contents of this matrix are added, then the result is compared to a predefined detection threshold. The compared data is the energy added after five consecutive cycles. If the result is less than the threshold, it is estimated that 0 is transmitted; otherwise, it is judged that 1 is sent.
5. Digital Implementation Using FPGA
After data is received, it is digitally processed using FPGA technology. The target FPGA family is a Xilinx Spartan IIE (XC2S200E) due to the availability of boards based on this family in our labs. In order to achieve high performance, pipelining technique was used. A block diagram of the FPGA implementation is shown in Figure 6. Even though the figure shows an example of eight channels, only five channels were implemented in hardware. However, our implementation can be generalized to any number of channels.
For an N-channel receiver, an addition is required every bit period T n , which is composed of N chip periods T c ; in addition, each T c seconds is composed of 16-bit stream. The addition is performed in a tree fashion (see Figure 6). Therefore, it takes cycles to sum N numbers (N channels). Since we need addition, the summation should be performed N times; that is cycles. However, by using pipelining technique, we were able to reduce the number of cycles for an addition to .
This high-speed implementation is achieved at the expense of adders. In order to reduce the area occupied by the design, serial adders were used. Even though the summation of 16-by-16 bits requires 16 cycles, the clock frequency achieved is several times higher than that of a parallel adder.
As an example, consider an 8-channel receiver (Figure 6). Every chip period T c eight 8-bit ADCs convert the received analog signals into eight bits, which are extended into 16 bits and shifted serially into eight 16-bit shift registers. The serial outputs from every two shift registers are fed into a serial adder, which will perform the summation and generate the sum of one bit at a time. The output of each adder is connected to the input of another 16-bit shift register in order to store the results of the summation. Each module (M-I) in Figure 6 corresponds to two shift registers at the input of an adder and another shift register connected to the output of the adder.
For this eight channels example, the proposed implementation consists of a three-stage pipeline that performs the addition in a tree fashion. After initially filling the pipeline stages (this requires 3 clock cycles), all pipeline stages will be performing similar tasks. For instance, every clock cycle, Stage 1 would be performing four summations on the newly received data from the ADCs, whereas Stage 2 would be doing two parallel summations on the already summed data from Stage 1 that corresponds to the older ADC conversion. At the same time, Stage 3 would be summing the results from Stage 2 of the previous data. After eight clock cycles, an output bit is generated based on a threshold comparison, and the accumulator register is cleared in order to start accumulating data for a new output bit. This process is repeated after each eight clock cycles.
Number of slices
138 out of 2352 5%
Number of slice flip flops
232 out of 4704 4%
Number of 4 input LUTs
86 out of 4704 1%
Max. clock frequency
6. Numerical Results and Measurments
In this paper, we have proposed a simple technique yet very efficient to implement a multirate/multiclass CDMA system based on a novel code overlapping procedure. A system model was presented and the SIR was derived. The block diagram of the transmitter and the receiver were presented and discussed. Moreover, an efficient FPGA-based transceiver implementation was shown. This implementation was efficient in terms of both speed and area. Using simple educational FPGA board of type Xilinx Spartan IIE (XC2S200E), the measurement results showed that the proposed system can achieve very good performance in the presence of MAI. Both simulation and measurements showed that it is possible to increase the transmission rate well beyond the nominal rate. On the other hand, simulation results reveal that our newly proposed OV-CDMA outperform the classical VPG-FFH-CDMA.
This paper was presented in part at the IEEE VTC 2004 and IEEE ISCAS 2006 conferences. This work was supported in part by the Lebanese CNRS under Grant CNRSL no. 4082.
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