Skip to main content

Advertisement

Noise and Spurious Tones Management Techniques for Multi-GHz RF-CMOS Frequency Synthesizers Operating in Large Mixed Analog-Digital SOCs

Abstract

This paper presents circuit techniques and power supply partitioning, filtering, and regulation methods aimed at reducing the phase noise and spurious tones in frequency synthesizers operating in large mixed analog-digital system-on-chip (SOC). The different noise and spur coupling mechanisms are presented together with solutions to minimize their impact on the overall PLL phase noise performance. Challenges specific to deep-submicron CMOS integration of multi-GHz PLLs are revealed, while new architectures that address these issues are presented. Layout techniques that help reducing the parasitic noise and spur coupling between digital and analog blocks are described. Combining system-level and circuit-level low noise design methods, low phase noise frequency synthesizers were achieved which are compatible with the demanding nowadays wireless communication standards.

[1234567891011121314151617181920212223242526272829303132]

References

  1. 1.

    Mijuskovic D, Bayer M, Chomicz T, et al.: Cell-based fully integrated CMOS frequency synthesizers. IEEE Journal of Solid-State Circuits 1994,29(3):271–279. 10.1109/4.278348

  2. 2.

    Young IA, Greason JK, Wong KL: A PLL clock generator with 5 to 10 MHz of lock range for microprocessors. IEEE Journal of Solid-State Circuits 1992,27(11):1599–1607.

  3. 3.

    Maxim A, Scott B, Schneider EM, Hagge ML, Chacko S, Stiurca D: A low-jitter 125–1250-MHz process-independent and ripple-poleless 0.18-m CMOS PLL based on a sample-reset loop filter. IEEE Journal of Solid-State Circuits 2001,36(11):1673–1683. 10.1109/4.962287

  4. 4.

    Maxim A: A 0.16–2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation. IEEE Journal of Solid-State Circuits 2005,40(1):110–131.

  5. 5.

    Maneatis JG: Low-jitter process-independent DLL and PLL based on self-biased techniques. IEEE Journal of Solid-State Circuits 1996,31(11):1723–1732. 10.1109/JSSC.1996.542317

  6. 6.

    Novof II, Austin J, Kelkar R, Strayer D, Wyatt S: Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and50 ps jitter. IEEE Journal of Solid-State Circuits 1995,30(11):1259–1266. 10.1109/4.475714

  7. 7.

    Lin L, Tee L, Gray PR: A 1.4 GHz differential low-noise CMOS frequency synthesizer using a wideband PLL architecture. Proceedings of IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC '00), February 2000, San Francisco, Calif, USA 204–205, 458.

  8. 8.

    Boerstler DW: A low-jitter PLL clock generator for microprocessors with lock range of 340–612 MHz. IEEE Journal of Solid-State Circuits 1999,34(4):513–519. 10.1109/4.753684

  9. 9.

    Maneatis JG, Kim J, McClatchie I, Maxety J, Shankaradas M: Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL. IEEE Journal of Solid-State Circuits 2003,38(11):1795–1803. 10.1109/JSSC.2003.818298

  10. 10.

    Lee J, Kim B: A low-noise fast-lock phase-locked loop with adaptive bandwidth control. IEEE Journal of Solid-State Circuits 2000,35(8):1137–1145. 10.1109/4.859502

  11. 11.

    Maxim A: A low voltage, 10–2550MHz, 0.15m CMOS, process and divider modulus independent PLL using zero-VT MOSFETs. Proceedings of the 29th European Solid-State Circuits Conference (ESSCIRC '03), September 2003, Estoril, Portugal 105–108.

  12. 12.

    Maxim A, Gheorghe M: A sub-1 jitter 1–5GHz 0.13m CMOS PLL using a passive feedforward loop filter with noiseless resistor multiplication [frequency synthesizer application]. Proceedings of IEEE Radio Frequency Integrated Circuits Symposium (RFIC '05), June 2005, Long Beach, Colo, USA 207–210.

  13. 13.

    Hajimiri A, Lee TH: A general theory of phase noise in electrical oscillators. IEEE Journal of Solid-State Circuits 1998,33(2):179–194. 10.1109/4.658619

  14. 14.

    Rael JJ, Abidi AA: Physical processes of phase noise in differential LC oscillators. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC '00), May 2000, Orlando, Fla, USA 569–572.

  15. 15.

    Maxim A, Turinici C: 9.953–12.5GHz 0.13m CMOS LC VCO using a high resolution calibration and a constant gain varactor. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC '05), September 2005, San Jose, Calif, USA 545–548.

  16. 16.

    Margarit MA, Tham JL, Meyer RG, Deen MJ: A low-noise, low-power VCO with automatic amplitude control for wireless applications. IEEE Journal of Solid-State Circuits 1999,34(6):761–771. 10.1109/4.766810

  17. 17.

    Zanchi A, Samori C, Lacaita AL, Levantino S: Impact of AAC design on phase noise performance of VCOs. IEEE Transactions on Circuits and Systems II 2001,48(6):537–547. 10.1109/82.943325

  18. 18.

    Rogers JWM, Rahn D, Plett C: A study of digital and analog automatic-amplitude control circuitry for voltage-controlled oscillators. IEEE Journal of Solid-State Circuits 2003,38(2):352–356. 10.1109/JSSC.2002.807401

  19. 19.

    Maxim A: A 2–5GHz low jitter 0.13m CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application]. Proceedings of the IEEE Custom Integrated Circuits Conference Digest of Technical Papers (CICC '04), October 2004, Orlando, Fla, USA 147–150.

  20. 20.

    Koo Y, Huh H, Cho Y, et al.: A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and Cellular-CDMA wireless systems. IEEE Journal of Solid-State Circuits 2002,37(5):536–542. 10.1109/4.997845

  21. 21.

    Shu K, Sánchez-Sinencio E, Silva-Martínez J, Embabi SHK: A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier. IEEE Journal of Solid-State Circuits 2003,38(6):866–874. 10.1109/JSSC.2003.811875

  22. 22.

    De Muer B, Steyaert MSJ: A CMOS monolithic-controlled fractional-N frequency synthesizer for DCS-1800. IEEE Journal of Solid-State Circuits 2002,37(7):835–844. 10.1109/JSSC.2002.1015680

  23. 23.

    Maxim A: A 9.953/10.7/12.5GHz 0.13m CMOS LC oscillator using capacitor calibration and a/R based low noise regulator. Proceedings of IEEE Radio Frequency Integrated Circuits Symposium (RFIC '05), June 2005, Long Beach, Colo, USA 411–414.

  24. 24.

    Hegazi E, Sjöland H, Abidi AA: A filtering technique to lower LC oscillator phase noise. IEEE Journal of Solid-State Circuits 2001,36(12):1921–1930. 10.1109/4.972142

  25. 25.

    Woyciehowsky S-P, Nottenburg RN: 10GHz LC-tuned VCO with coarse and fine frequency control. Electronics Letters 1997,33(11):917–918. 10.1049/el:19970654

  26. 26.

    Kral A, Behbahani F, Abidi AA: RF-CMOS oscillators with switched tuning. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC '98), May 1998, Santa Clara, Calif, USA 555–558.

  27. 27.

    Sidiropoulos S, Acharya N, Chau P, et al.: An 800 mW 10 Gb Ethernet transceiver in 0.13m CMOS. Proceedings of IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC '04), February 2004, San Francisco, Calif, USA 1: 168–520.

  28. 28.

    Lizhang S, Nelson D: A 1.0 V GHz range 0.13m CMOS frequency synthesizer. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC '01), May 2001, San Diego, Calif, USA 327–330.

  29. 29.

    Maxim A: A multi-rate 9.953–12.5-GHz 0.2-m SiGe BiCMOS LC oscillator using a resistor-tuned varactor and a supply pushing cancellation circuit. IEEE Journal of Solid-State Circuits 2006,41(4):918–934.

  30. 30.

    Su J-G, Hsu H-M, Wong S-C, Chang C-Y, Huang T-Y, Sun JY-C: Improving the RF performance of 0.18m CMOS with deep n-well implantation. IEEE Electron Device Letters 2001,22(10):481–483. 10.1109/55.954918

  31. 31.

    Kosaka D, Nagata M, Hiraoka Y, et al.: Isolation strategy against substrate coupling in CMOS mixed-signal/RF circuits. Proceedings of 18th International Conference on VLSI Circuits (VLSI '05), June 2005, Kyoto, Japan 276–279.

  32. 32.

    Maxim A: A 10Gb/s SiGe compact laser diode driver using push-pull emitter followers and miller compensated output switch. Proceedings of the 29th European Solid-State Circuits Conference (ESSCIRC '03), September 2003, Estoril, Portugal 557–560.

Download references

Author information

Correspondence to Adrian Maxim.

Rights and permissions

Reprints and Permissions

About this article

Cite this article

Maxim, A. Noise and Spurious Tones Management Techniques for Multi-GHz RF-CMOS Frequency Synthesizers Operating in Large Mixed Analog-Digital SOCs. J Wireless Com Network 2006, 024853 (2006). https://doi.org/10.1155/WCN/2006/24853

Download citation

Keywords

  • Phase Noise
  • Noise Frequency
  • Noise Performance
  • Frequency Synthesizer
  • Analog Block