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  • Research Article
  • Open Access

Design and Characterization of a 5.2 GHz/2.4 GHz Fractional- Frequency Synthesizer for Low-Phase Noise Performance

  • 1Email author,
  • 2,
  • 1 and
  • 3
EURASIP Journal on Wireless Communications and Networking20062006:048489

Received: 8 August 2005

Accepted: 13 January 2006

Published: 15 March 2006


This paper presents a complete noise analysis of a -based fractional- phase-locked loop (PLL) based frequency synthesizer. Rigorous analytical and empirical formulas have been given to model various phase noise sources and spurious components and to predict their impact on the overall synthesizer noise performance. These formulas have been applied to an integrated multiband WLAN frequency synthesizer RFIC to demonstrate noise minimization through judicious choice of loop parameters. Finally, predicted and measured phase jitter showed good agreement. For an LO frequency of 4.3 GHz, predicted and measured phase noise was rms and rms, respectively.


  • Phase Noise
  • Noise Source
  • Base Frequency
  • Noise Performance
  • Noise Analysis


Authors’ Affiliations

Carleton University, Ottawa, Canada
Electrical and Computer Engineering Department, Auburn University, Auburn, USA
Alereon, Inc., Austin, USA


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© John W. M. Rogers et al. 2006

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.