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Design and Characterization of a 5.2 GHz/2.4 GHz Fractional- Frequency Synthesizer for Low-Phase Noise Performance

EURASIP Journal on Wireless Communications and Networking volume 2006, Article number: 048489 (2006) Cite this article

Abstract

This paper presents a complete noise analysis of a-based fractional- phase-locked loop (PLL) based frequency synthesizer. Rigorous analytical and empirical formulas have been given to model various phase noise sources and spurious components and to predict their impact on the overall synthesizer noise performance. These formulas have been applied to an integrated multiband WLAN frequency synthesizer RFIC to demonstrate noise minimization through judicious choice of loop parameters. Finally, predicted and measured phase jitter showed good agreement. For an LO frequency of 4.3 GHz, predicted and measured phase noise was rms and rms, respectively.

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Authors and Affiliations

  1. Carleton University, 1125 Colonel Drive, Ottawa, ON, Canada, K1S 5B6

    John WM Rogers & Calvin Plett

  2. Electrical and Computer Engineering Department, Auburn University, Auburn, AL, 36849-5201, USA

    Foster F Dai

  3. Alereon, Inc., 7600 North Capital of Texas Highway, Building C, Suite 200, Austin, TX, 78731, USA

    MarkS Cavin

Authors
  1. John WM Rogers
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  2. Foster F Dai
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  3. Calvin Plett
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  4. MarkS Cavin
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Correspondence to John WM Rogers.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License ( https://creativecommons.org/licenses/by/2.0 ), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Rogers, J.W., Dai, F.F., Plett, C. et al. Design and Characterization of a 5.2 GHz/2.4 GHz Fractional- Frequency Synthesizer for Low-Phase Noise Performance. J Wireless Com Network 2006, 048489 (2006). https://doi.org/10.1155/WCN/2006/48489

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  • DOI: https://doi.org/10.1155/WCN/2006/48489

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