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Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling

Abstract

Ultra-wideband (UWB) impulse radios show strong advantages for the implementation of low-power transceivers. In this paper, we analyze the impact of CMOS technology scaling on power consumption of UWB impulse radios. It is shown that the power consumption of the synchronization constitutes a large portion of the total power in the receiver. A traditional technique to reduce the power consumption at the receiver is to operate the UWB radios with a very low duty cycle on an architecture with extreme parallelism. On the other hand, this requires more silicon area and this is limited by the leakage power consumption, which becomes more and more a problem in future CMOS technologies. The proposed quantitative framework allows systematic use of digital low-power design techniques in future UWB transceivers.

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Correspondence to Mustafa Badaroglu.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License ( https://creativecommons.org/licenses/by/2.0 ), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Badaroglu, M., Desset, C., Ryckaert, J. et al. Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling. J Wireless Com Network 2006, 072430 (2007). https://doi.org/10.1155/WCN/2006/72430

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Keywords

  • Power Consumption
  • Duty Cycle
  • Total Power
  • Traditional Technique
  • CMOS Technology