Residue code based low cost SEUtolerant fir filter design for OBP satellite communication systems
 Wenhui Yang^{1},
 Zhen Gao^{2},
 Xiang Chen^{3}Email author,
 Ming Zhao^{2} and
 Jing Wang^{2}
https://doi.org/10.1186/168714992012174
© Yang et al; licensee Springer. 2012
Received: 15 November 2011
Accepted: 18 May 2012
Published: 18 May 2012
Abstract
With the development of satellite communications, onboard processing (OBP) obtains more and more attentions due to the increased efficiency and performance. However, the large amounts of digital circuits in the OBP transponders are sensitive to the highenergy particles in space radiation environments, which may cause various kinds of single event effect. Among these effects, single event upset (SEU) is the major potential reason for the instability of the satellite communication systems. Triple modular redundancy (TMR) is a classical and effective method for mitigating the SEU in digital circuits. However, since three identical logic modules and a voting circuit are needed in TMR, the overhead is so high that the scheme may not be applicable on the onboard digital processing platform with very limited area and power resources. Therefore, how to design a more costeffective faulttolerant method becomes a critical issue. Considering that FIRlike processing is frequently used on OBP platform, in this article, a dual modules (DM) plus checking module based on residue code (DMCRC) architecture for SEUtolerant FIR design is proposed. Although this architecture reduces the area overhead dramatically, we find that the fault missing rate is still high if singlesample checking (SSC) is used. To solve this problem, a Multisample checking DMCRC (MSCDMCRC) is further proposed. Our analysis shows that the MSCDMCRC scheme can make the fault missing rate small enough without reducing the actual throughput. By simulations it is shown that, when the modulus for CRC is 7 and the number of samples for MSC is 4, the reduction of area overhead relative to TMR is over 20% and the fault missing rate is as low as 0.05%.
Keywords
1 Introduction
Traditional bent pipe (BP) satellite performs only signal amplification and frequency translation. However, with the development of satellite communication applications, the demand for communication quality and capacity has increased so rapidly that BP transponders cannot afford. Instead, the onboard processing (OBP) becomes the inevitable alternative [1]. The goals of OBP are to provide singlehop connectivity to small earth station, and to enhance link performance and efficiency [2]. Compared to the twohop connection in BP systems, singlehop connection decreases the oneway transmission delay from 540 to 270 ms, which provides more comfortable user experience. The enhanced performance by OBP can be used to reduce the cost of small earth stations [3] or increase the system capacity.
The OBP directly related to communications can be roughly divided into two classes: intermediate/radio frequency (IF/RF) processing and switching and baseband OBP [2, 3]. The IF/RF processing and switching is actually the digital channelization technique [4–6]. As an intermediate during the development from BP towards the software defined fully processed payload, digital channelization realizes the demultiplexing, switching and multiplexing of subchannels, without fully decoding of the information in the subchannels [7]. Since digital channelization maintains the transparence to the physical layer transmission techniques as BP, and provides much better performance over BP, it is widely used by many successful mobile satellite communication systems, including ACeS [8], Thuraya [9], WGS [10, 11] and MOUS [12, 13]. In consideration of the necessity of FIR filters and FFT for digital channelization [14, 15], they are considered as the most basic and important modules on digital channelizing OBP.
Baseband OBP is commonly referred as fully processing satellite platform, so all the physical layer techniques, including demodulation/modulation, decoding/encoding and channel estimation/equalization, should be performed for the signal regeneration for each subchannel [3, 14]. The Thuraya system is a good example of current satellite communication systems with baseband OBP platform [9]. Since complete switching is required in baseband OBP, FIR and FFT are still the basic modules. As introduced in [3, 16, 17], the orthogonal frequency division multiplexing (OFDM) technology is a very attractive candidate when targeting high quality and high flexibility in future mobile multimedia satellite communications systems, so FFT is still a necessary module. In addition, almost all the current mobile satellite communication systems (e.g. ACeS, Thuraya, WGS, MOUS, and so on) and future ones, no matter digital channelization or fully processed baseband OBP, would apply digital beamforming (DBF) for multiplebeam coverage [8–13], so DBF is also a necessary DSP module on OBP platforms [18, 19].
SRAMFPGA is a good option for OBP implementation because of its high density, high performance, reduced development cost and reconfigurability, the last of which is quite useful for remote update and maintenance of the OBP satellite systems [20]. However, SRAMFPGA based systems, including memories and logics, are sensitive to the radiation in space environments, so they are not reliable enough for spatial applications without any protection. single event upset (SEU) is one of the main radiation effects, and induces the majority of the function faults on OBP platform [21]. Therefore, the SEUtolerant scheme is the key issue for the feasibility of the SRAMFPGA based applications on OBP platforms.
As a classical faulttolerant solution, triple modular redundancy (TMR) applies three identical modules to perform the same process, and the results are processed by a majority voter to produce a single output. So if only one of the three modules fails, the other two can help to mask the faults [22]. However, TMR introduces tripled space, weight and power, which result in impossibility to implement on the satellite platforms where resources are limited. For example, space based radar requires 100's of giga floating point operation's of OBP and 10's of Gbps data links to accomplish mission goals [23]. A TMR approach for such a program would create a system that weighs hundreds of pounds and requires kilowatts of power, which are unbearable for an OBP platform [23]. Thus, for onboard applications, the lowcost faulttolerant designing is in demand.
in which x(l) and h(l), l = 0, 1, ..., L  1 are input data for the current operation and coefficients, respectively. Since only multiplications and additions are involved, this structure is called multiply and accumulation (MAC). The reason we choose MAC as our target is that it is the general structure of the common used DSPs in OBP, such as FIR, FFT and DBF. For FIR, h(l) is the filter coefficients. For FFT, h(l) is the rotation factor. And for DBF, h(l) is the weighting coefficient. To facilitate the description and analysis, this article will focus on the SEUtolerant FIR design. The analysis method and theoretical results can be easily applied to other DSPs with MAC structure.
 (1)
A simple DM plus checking module based on residue code (DMCRC) structure is proposed to reduce the heavy cost of traditional TMR method;
 (2)
The fault missing problem of general residue code based checking module is revealed;
 (3)
Finally, we propose a multisample checking (MSC) solution to decrease the fault missing rate.
The rest of this article is organized as follows. In Section 2, related work and mathematical background are given. In Section 3, the singlesample checking based DMCRC (SSCDMCRC) faulttolerant scheme is proposed, and its fault missing rate analysis for the modulus with different form is given. Section 4 introduces the MSC based DMCRC(MSCDMCRC) scheme to reduce the missing rate of the SSCDMCRC. Simulation results to validate our theoretical analysis are given in Section 5. Section 6 concludes this article.
2 Related work and mathematical background
Many faulttolerant schemes based on residue code have been proposed to reduce the overhead of TMR for FIR design. Before introducing these schemes, the property of residue code and residue number system (RNS) is introduced firstly.
where m is the modulus and op represents the linear operator.
Based on RNS, a scheme named redundant RNS (RRNS) [26, 27] is proposed for fault tolerant of single branch. In RRNS, redundant branches with new modulus are added to the original RNS system. With the dynamic range maintained, if one of the branches fails because of SEU, the correct result can still be recovered from other branches. Since only redundant branches with simplified computations are added, the SEUtolerant overhead of RRNS is much smaller than that of TMR. The problem of RRNS is that several CRT modulus are added for fault detection of parallel computation branches, but the CRT modulus themselves are not protected from SEU. If TMR is applied for CRT, the advantage of low overhead will disappear.
Onetoone mapping of arithmetic error and syndromes for A_{1} = 7 A_{2} = 15 [29]
j  { 2^{ j }_{7}}, { 2^{ j }_{15}}  { 2^{ j }_{7}}, { 2^{ j }_{15}} 

0  (1,1)  (6, 14) 
1  (2,2)  (5, 13) 
2  (4,4)  (3, 11) 
3  (1,8)  (6, 7) 
4  (2,1)  (5, 14) 
5  (4,2)  (3, 13) 
6  (1,4)  (6, 11) 
7  (2,8)  (5, 7) 
8  (4,1)  (3, 14) 
9  (1,2)  (6, 13) 
10  (2,4)  (5, 11) 
11  (4,8)  (3, 7) 
But there are three important issues neglected in [29]. Firstly, the correct logic is only effecitve for single bit error in the outputs. Actually, this kind of errors occupies only a small part of the fault models. When single error occurs in the intermediate data, multiple bits may upset in the output. For example, for binary computation 11 * 1000 = 11000, when "1000" turns into "1001" by SEU, we obtain 11 * 1001 = 11011. Obviously, two bits are upset in the result, which cannot be corrected by the correction method proposed in [29]. Secondly, the case that an error occurs in the checking module is not taken into account in [29]. What's more, the fault missing problems are also ignored in [29].
It should be noticed that, all the faulttolerant designs mentioned above behave in such a way that a decision is made for each output. This approach is called SSC in this article.
3 SSC based DMCRC
Aiming at the problems of the two residue code based schemes mentioned in Section 2, a new residue code based faulttolerant architecture is proposed in this section, and the fault missing rate is analyzed in detail.
3.1 Architecture and working procedure of SSC based DMCRC
 (1)If y _{1} = y _{2}, y _{1} is chosen as the output y = y _{1}. At the same time, (y _{1})_{ m }is used to check whether CRC module runs correctly. Two cases may be met here:
 (a)
(y _{1})_{ m }= r: the checking module runs correctly and no action is taken;
 (b)
(y _{1})_{ m }≠ r: an SEU occurs in the checking module, so it should enter the recovery process.
 (a)
 (2)If y _{1} ≠ y _{2}, r is used to check (y _{1})_{ m }and (y _{2})_{ m }according to Equation (2). Four cases may be met here:
 (a)
(y _{1})_{ m }= r and (y _{2})_{ m }≠ r: y _{1} is output and M _{2} enters the recovery process;
 (b)
(y _{1})_{ m }≠ r and (y _{2})_{ m }= r: y _{2} is output and M _{1} enters the recovery process;
 (c)
(y _{1})_{ m }= r and (y _{2})_{ m }= r: an error happened, but the checking module cannot identify it, so y _{1} or y _{2} is chosen randomly as the output. In this case y _{1} and y _{2} are called congruent samples.
 (d)
(y _{1})_{ m }≠ r and (y _{2})_{ m }≠ r: it means more than one branches fail. This case is out of the range of this article.
 (a)
The recovery processing mentioned in (1)b, (2)a and b is used to avoid SEU accumulation in the system, and can be accomplished by scrubbing (or reconfiguration) [30]. (2)c is actually the fault missing event, which is the key problem for residue code based checking and has been ignored in DWCCED and "FIR plus two CRCs". As mentioned above, an SEU in SRAMFPGA may not only change the data stored in a memory unit, but may also change the function logic. In this article, we assume that the result of logic damage is always so serious that (2)b will happen, so the fault missing event is only caused by SEU in a memory unit. In the following subsections, this fault missing rate for Ltap FIR filters is analyzed.
3.2 Analysis of the fault missing rate for SSCDMCRC
3.2.1 Fault models
In this section, only the basic FIR filters composed of MAC units are considered for the analysis of fault missing rate. Before studying on the performance of SEUtolerant systems, the SEU fault models are established firstly in this subsection.
where x_{ l }is the l th input, h_{ l }is the l th coefficients, l = 0,1, ..., L  1. Since FIR filters are composed of MAC units, the fault model can be classified into multiplierinput fault (MIF) model and adderinput fault (AIF) model.
Equations (7) and (8) will be used for fault missing rate analysis in following subsections.
3.2.2 Computation of fault missing rate for MIF model
The cases leading to (x_{ l }* 2^{ q })_{ m }= 0 include the following three cases:

Case A: (x_{ l })_{ m }= 0;

Case B: (2^{ q })_{ m }= 0, (x_{ l })_{ m }≠ 0;

Case C: (x_{ l })_{ m }≠ 0, (2^{ q })_{ m }≠ 0, but (x_{ l })_{ m }* (2^{ q })_{ m }= km, where k is a natural number.
For (x_{ l })_{ m }, we proved by simulation (not given in this article due to page limited) that, for random inputs x_{ l }with Gaussian, Rayleigh or Rician distribution, (x_{ l })_{ m }is uniformly distributed between 0 and m  1, or (x_{ l })_{ m }~ U[0, m 1].
The analysis of Equation (11) is directly related to the value of m. According to [31], due to low complexity for implementation, 2^{ n }and 2^{ n }± 1 are the most common choice for m, so this subsection will focus on the analysis of P_{m _MIF}when m = 2^{ n }or 2^{ n }± 1, respectively.
 (1)
If q ≥ n, (2^{ q })_{ m }= 0 is always true, so Case B causes P _{m _MIF}= 1, which means the SEU on a bit that is higher than n will never be identified for m = 2^{ n }.
 (2)If q < n, (2^{ q })_{ m }≠ 0 always holds, so Cases A and C are considered. For Case A, (x _{ l })_{ m }is always uniform distributed on [0,m  1], so $\text{Prob}\left({\left({x}_{l}\right)}_{m}=0\right)=\frac{1}{m}=\frac{1}{{2}^{n}}$. For Case C, as 2^{ q }< m = 2^{ n }, we have (2^{ q })_{ m }= 2^{ q }. If (x _{ l })_{ m }* (2^{ q })_{ m }= km (k ∈ N), we obtain (x _{ l })_{ m }= k* 2^{nq}. As mentioned above, (x _{ l })_{ m }∈ [1, 2^{ n } 1], thus, the number of value of (x _{ l })_{ m }that makes (x _{ l })_{ m }* (2^{ q })_{ m }= km, or the number of k ∈ N satisfying (x _{ l })_{ m }* (2^{ q })_{ m }= km, should be $\u230a\frac{{2}^{n}1}{{2}^{nq}}\u230b={2}^{q}1$. For example, when n = 4(m = 16), if q = 1, (2^{ q })_{ m }= 2, so only (x _{ l })_{ m }= 8 can make (x _{ l })_{ m }* (2^{ q })_{ m }= 16 for k = 1; if q = 2, (2^{ q })_{ m }= 4, (x _{ l })_{ m } = 4, 8 and 12 can make (x _{ l })_{ m }* (2^{ q })_{ m }= 16, 32 and 48 for k = 1, 2 and 3, respectively. Since the probability for each value of (x _{ l })_{ m }= k* 2^{nq}is $\frac{1}{{2}^{n}}$, the fault missing rate for Case C can be calculated as (2^{ q } 1)/2^{ n }. Actually, if we consider Case A and a special case of Case C for k = 0, the combined case becomes (2^{ q })_{ m }≠ 0, (x _{ l })_{ m }* (2^{ q })_{ m }= km, k ∈ Z, k ≥ 0, and it's easy to find out that the fault missing rate for this case is 2^{ q }/2^{ n }for q < n. In summary, for m = 2^{ n }, the fault missing rate under MIF model can be expressed as${P}_{m\text{\_}\text{MIF}}^{{2}^{n}}=\left\{\begin{array}{cc}\hfill \frac{{2}^{q}}{{2}^{n}},\hfill & \hfill q<n;\hfill \\ \hfill 1,\hfill & \hfill q\ge n.\hfill \end{array}\right.$(12)
 (1)
If q ≤ n, we have (2^{ q })_{ m }= 2^{ q }, so the value of k for (x _{ l })_{ m }* (2^{ q })_{ m }= km should be (x _{ l })_{ m }* 2^{ q }/(2^{ n }± 1), which is not an integer since the denominator cannot be the factor of the numerator;
 (2)
If q > n, we have (2^{ q })_{ m }= 2^{ q } p(2^{ n }± 1), where p is a natural number, so the k for (x _{ l })_{ m }* (2^{ q })_{ m }= km is $\frac{{\left({x}_{l}\right)}_{m}*\left({2}^{q}p\left({2}^{n}\pm 1\right)\right)}{{2}^{n}\pm 1}=\frac{{\left({x}_{l}\right)}_{m}*{2}^{q}}{{2}^{n}\pm 1}{\left({x}_{l}\right)}_{m}p$, which is neither an integer since $\frac{{\left({x}_{l}\right)}_{m}*{2}^{q}}{{2}^{n}\pm 1}$ is not an integer.
3.2.3 Computation of fault missing rate for the AIF model
According to (14), for m = 2^{ n }, when q < n, (2^{ q })_{ m }= 2^{ q }, so ${P}_{m\text{\_}\text{AIF}}^{{2}^{n}}=\text{Prob}\left({\left({2}^{q}\right)}_{m}=0\right)=0$. Otherwise, when q ≥ n, (2^{ q })_{ m }= 0 always holds, so ${P}_{m\text{\_}\text{AIF}}^{{2}^{n}}=\text{Prob}\left({\left({2}^{q}\right)}_{m}=0\right)=1$.
Furthermore, for m = 2^{ n }± 1, (2^{ q })_{ m }≠ 0, so ${P}_{m\text{\_}\text{AIF}}^{{2}^{n}+1}=0$.
Based on the above analysis, although the implementation of CRC with m = 2^{ n }is the simplest, the fault missing rate is much higher than that with m = 2^{ n }± 1 for both fault models, so we conclude that m = 2^{ n }is not suitable for CRC. On the other hand, the CRC with m = 2^{ n }± 1 achieves much smaller fault missing rate with negligible implementation overhead. So the analysis in Section 4 will focus on the CRC with m = 2^{ n }± 1.
4 MSC based DMCRC
This section proposes a solution to the fault missing problem of SSCDMCRC and analyzes the related fault missing rate.
4.1 Working procedure of MSC based DMCRC
It should be emphasized that, since the buffered outputs of the faultfree module are output as a block, the equivalent throughput maintains unchanged during the MSC processing.
4.2 Analysis of the fault missing rate for MSCDMCRC
which equals to (2^{ n }± 1)^{N}for m = 2^{ n }± 1. The simulations in Section 5 will show that n = 3, N = 4 can ensure the ${P}_{m\text{MSC}}^{{2}^{n}\pm 1}$ as low as 0.05% in practice.
Considering that the unrecognizable faults for MSC are mainly from the samples at the end of the filtering procedure, e.g. l = L  1 or L  2, the registers storing these samples should be taken as "VIPs" and hardened by individual protection, such as TMR.
Now the hybrid scheme combining MSC and TMR can guarantee a low fault missing rate, even the SEU happens on input samples.
5 Simulation results
In this section, FPGA based fault injections are performed to show the overhead reduction of the DMCRC architecture relative to the TMR, and to validate the fault missing analysis for the SSCDMCRC and MSCDMCRC based FIR designs in Sections 3 and 4. In the simulations, a 16tap FIR filter with 8bit inputs and 8bit coefficients are implemented in ISE12.3 for Xilinx FPGA Virtex4 XC4VLX100.
Overhead comparison
Logic utilization  TMR protected  Proposed method protected  

n = 2  n = 3  n = 4  n = 5  n = 6  
Number of slices  1085  742  846  902  1028  1089 
Slice flip flops  1533  1008  1142  1156  1233  1272 
4input LUTs  1537  1175  1344  1453  1535  1892 
Since the properties of fault missing rate are similar for m = 2^{ n }± 1, the simulations for m = 2^{ n }+ 1 are not given here. It should be pointed out that, the numerical results given in this section are only based on the basic implementation of a 16tap FIR filter, and other FIR implementations may produce different results. However, our analysis method and the general conclusions given in this article should hold for all CRC based SEUtolerant FIR designs.
6 Conclusion
To reduce the area and power overhead of TMR protected on board processing (OBP) transponders, a simple and effective SEUtolerant design is proposed for the basic FIR implementation. The design is based on a structure with DM of normal FIR and one DMCRC. The fault missing problem, which is common for residue code based checking schemes, is firstly revealed in this article, and the fault missing rate for SSC is analyzed in detail based on the DMCRC structure. Then, the MSC is proposed to solve the fault missing problem. The MSCDMCRC based FIR design achieves smaller overhead and lower fault missing rate simultaneously. Fault injection campaigns show that, for a 16tap FIR filter with 8bit input samples and coefficients, if the modulus for checking branch is 7 and the buffering length is 4, the proposed MSCDMCRC FIR design can save more than 20% area overhead relative to the TMR design, and the fault missing rate can be reduced to 0.05%. The analysis method and theoretical results can also be applied to the SEUtolerant design of other OnBoard DSPs with MAC structure, such as FFT and digital beamforming.
Acknowledgements
This work was supported by National Basic Research Program of China (2012CB316002), National S&T Major Project (2011ZX03004004) and Tsinghua Research Funding.
Declarations
Authors’ Affiliations
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