Table 1 Timing diagram
From: Design and implementation of real time wideband channel simulator
Time Line → | 0 | NT s | 2NT s | 3NT s |
|---|---|---|---|---|
EDMA Transfer | ADC→PING IN | PONG OUT→DAC | ADC→PONG IN | PING OUT→DAC |
DSP Processes | IDLE | PING BUFF | IDLE | PONG BUFF |
From: Design and implementation of real time wideband channel simulator
Time Line → | 0 | NT s | 2NT s | 3NT s |
|---|---|---|---|---|
EDMA Transfer | ADC→PING IN | PONG OUT→DAC | ADC→PONG IN | PING OUT→DAC |
DSP Processes | IDLE | PING BUFF | IDLE | PONG BUFF |