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An adaptive lowpower LDPC decoder using SNR estimation
EURASIP Journal on Wireless Communications and Networking volume 2011, Article number: 48 (2011)
Abstract
Owing to advancement in 4 G mobile communication and mobile TV, the throughput requirement in digital communication has been increasing rapidly. Thus, the need for efficient errorcorrecting codes is increasing. Furthermore, since most mobile devices operate with limited battery power, lowpower communication techniques are attracting considerable attention lately. In this article, we propose a novel lowpower, lowdensity parity check (LDPC) decoder. The LDPC code is one of the most common errorcorrecting codes. In mobile TV, SNR estimation is required for the adaptive coding and modulation technique. We apply the SNR estimation result to the proposed LDPC decoding to minimize power consumption due to unnecessary operations. The SNR estimation value is used for predicting the iteration count until the completion of the successful LDPC decoding. When the SNR value is low, we omit computing the parity check and the tentative decision. We implemented the proposed decoder which is capable of adaptively skipping unnecessary operations based on the SNR estimation. The power consumption was measured to show the efficiency of our approach. We verified that, by using our proposed method, power consumption is reduced by 10% for the SNR range of 1.52.5 dB.
1. Introduction
Recent advances in 4 G mobile communication systems require reliable high transmission rates. The bandwidth requirement for high speed 4 G information transfer is 100 Mbps, while the requirement for lowspeed or stationarystate transfer is 155 Mbps1 Gbps. Thus, the use of powerful errorcorrecting codes is crucial for the next generation mobile communication system [1]. Lowdensity parity check (LDPC) decoding has become especially relevant because of its excellent error correcting capability.
LDPC codes are linear block codes that were originally introduced by Gallager [2] in 1962. During that time, they attracted little attention, since hardware implementation of such decoding was impractical in the 1960s, and has been neglected since. However, the value of LDPC codes was rediscovered by Mackay and Neal in 1995, and many subsequent studies have shown that LDPC probabilistic decoding is very effective [3, 4]. Recently, Chung et al. [5] showed that LDPC codes can come within 0.0045 dB of the Shannon limit. Turbo code was regarded as the best channelcoding technique before the rediscovery of LDPC, but LDPC codes have a smaller minimum distance than Turbo codes. LDPC codes exhibit very good BER curves, because they suffer from minimal error floor issues. Furthermore, iterative LDPC decoding schemes based on the SumProduct algorithm [6] can be fully parallelized, leading to highspeed decoding [7]. For these reasons, LDPC codes are very attractive for highspeed 4 G wireless communication. Currently, DVBS2, which is an European highquality digital satellite broadcasting standard, features the concatenation of LDPC codes with BCH codes as their channelcoding scheme [8].
Dynamic power consumption of a module is proportional to the amount of switching activities. With a low SNR, the received signal may not be successfully decoded before the maximum number of iterations is reached, and the corresponding decoding may consume a great amount of power. On the contrary, at a high SNR, the decoding may succeed with a fewer number of iterations before the predefined maximum number of iterations is tried. Therefore, it is important to accurately estimate SNR values to achieve highspeed, lowpower decoding. For excellent BER performance, both the size of the block and the maximum number of decoding iterations should be large. Decoding large blocks requires significant amounts of computation and memory. In addition, decoding latency as well as power consumption will increase significantly, in turn, creating a significant decrease in communication bandwidth [4, 9]. Recent studies have focused on lowering power consumption by adjusting either the maximum number of iterations or the quantization level according to estimated SNR values [10–12]. In this article, we propose a novel adaptive architecture that selectively carries out the tentative decision and paritycheck operations depending on estimated SNR values to reduce power consumption.
The remainder of this article is organized as follows. In Section 2, a typical decoding algorithm and principles of LDPC decoding with adaptive coding and modulation (ACM) are presented. A novel, lowpower LDPC decoding algorithm is presented in Section 3. In Sections 4 and 5, we present a performance evaluation of our novel design. Section 6 concludes this article.
2. Background
2.1. LDPC decoding algorithms
LDPC codes are linear block codes based on a paritycheck matrix called an Hmatrix, in which rows and columns represent paritycheck codes and symbols, respectively. The Hmatrix can be equivalently represented by a Tanner graph, a bipartite graph in which one partite has check nodes and the other has bit nodes. The check nodes correspond to the rows of the Hmatrix, while the bit nodes correspond to the columns of the Hmatrix. An Hmatrix and the equivalent Tanner graph for an illustrative (10, 5) code are shown in Figures 1 and 2, respectively [6].
A conventional LDPC decoding algorithm is shown in Algorithm 1. Decoding is carried out iteratively in such a way that adjacent nodes in the Tanner graph exchange probabilities for the received codeword as shown in Figure 2. Decoded code words are checked against the Hmatrix as shown in Step 9 of Algorithm 1. If the paritycheck equation is satisfied (H C^{T} = 0), the decoding ends successfully even before the predefined maximum number of iterations is reached [13].
2.2. Adaptive coding and modulation
In the ACM architecture, the data from a base station are transmitted after channel coding, interleaving, and modulation are processed. The receiver first estimates the channel state information with the received signal and then sends the estimation result back to the sender. The channel state estimation is typically performed according to the SNR value. The sender determines the modulation and coding scheme (MCS) [8] level based on this information and adaptively applies channel coding, interleaving, and modulation methods according to the channel state for the upcoming transmission. ACM techniques typically result in better transmission rates with smaller error rates than typical coding and modulation techniques, since the proper MCS level is determined based on the estimated channel state. Currently, standards for mobile multimedia services such as DVBS2 and DVBT2 employ ACM techniques. In ACM, accurate channel state estimators are crucial [14]. We used experimental results to identify the best channel estimator, and propose a new adaptive decoding algorithm that utilizes information provided by this accurate channel state estimator (Figure 3).
3. Proposed LDPC decoder
The overall performance of LDPC decoding depends significantly on the number of decoding iterations. Large numbers of iterations may result in unacceptably long delays that may, in turn, lead to failures in realtime processing. Therefore, programmers typically set a limit on the maximum number of iterations allowed by LDPC. If the paritycheck equation is satisfied, decoding is completed even before the maximum number of iteration is reached.
In our novel decoder, we carry out the paritycheck operation only if SNR estimates fall within a certain range. In this way, we reduce power consumption and decoding latency. As discussed in the previous section, our proposed scheme is very efficient because it does not require any additional hardware.
3.1. Architecture of the proposed LDPC decoder
The architecture of the proposed LDPC decoder is shown in Figure 4. The sender inserts the start of frame (SOF) into the encoded signal, and the receiver estimates the SNR. The estimated SNR information is provided to the LDPC decoder to determine whether the parity check and the tentative decision will be computed. An accurate estimation of SNR is crucial for the proposed adaptive paritycheck scheme to succeed. To identify the best estimation algorithm, we assessed the accuracies of the two existing algorithms which are known to be reliable. First, the accuracy of the maximum likelihood (ML) algorithm (Equation 8), which is adequate for a short SOF as in the case of the DVBS2 standard, was measured. Second, the accuracy of the signaltonoise variance (SNV) (Equation 9) algorithm [15], which is a special case of the ML algorithm, was measured. In this experiment, we assumed a SOF of 26 symbols, as used in DVBS2. In Equations 8 and 9, c is the value of pilot symbols defined in SOF, and the receiver already knows the value. By using the correlation between c value and the received value r, SNR values are estimated.
Figure 5 shows the results of SNR estimation. We decided to use the SNV algorithm as our SNR estimation algorithm since it outperforms the ML algorithm with respect to mean square error (MSE). As mentioned earlier, an SNR estimator is required for ACM. It should be noted that this estimator is not necessary for our proposed adaptive parity check, but it is only necessary for ACM, which requires SNR estimation. Therefore, we believe that our scheme can improve decoding performance without incurring any overhead in terms of hardware.
3.2. Adaptive parity check by SNR estimation
We assessed the number of decoding iterations associated with various SNR values to see how the number of iterations changes according to the SNR value. Table 1 summarizes the result after we carried out a simulation of 1,000,000 frame data for a rate1/2 LDPC code with a block length of 9216 and a dimension of 4608 (CMMB code rate = 1/2 code) [16]. For each SNR value, we assessed the average number of iterations and the minimum number of iterations.
When SNR values were low, high iteration counts were necessary, whereas when SNR values were high, low iteration counts were sufficient. Hence, the tentative decision and the paritycheck equation need not be computed until we obtain a reasonable SNR value after a certain number of iterations.
A conventional modified UMPBP algorithm computes the tentative decision and the paritycheck equation after every iteration (Figure 6). According to Table 1 when the SNR is 2 dB, the iteration should be repeated at least six times. Therefore, it is not meaningful to compute the tentative decision and the parity check equation until this minimum number of iterations is achieved. Computing unnecessary values will increase both the decoding delay and the amount of power consumed. In our proposed scheme, based on the SNR, we store the minimum number of iterations in a lookup table to selectively carry out the parity check step. By this method, we may postpone computing the tentative decision and the parity check equation until the predetermined minimum number of iterations is reached. Our proposed scheme is summarized in Algorithm 2.
Conventionally, a paritycheck operation is conducted at every decoding iteration step. However, in Algorithm 2, the paritycheck operation is carried out only at the predetermined iteration count based on the predicted SNR as shown in Figure 7.
The lowpower technique proposed in the article requires an accurate SNR estimation. As Table 1 shows, the valid SNR range where the LDPC decoding can be carried out is greater than or equal to 1.5 dB. Experimental results in Figure 5 show that when the SNR is greater than or equal to 1.5 dB, the error range is 02 dB. The results show that the range of the minimal iteration count according to the SNR will be from 1 through 10, and the difference in the iteration counts for each SNR value is on average less than 3. Therefore, the proposed lowpower method cannot only work correctly, but also reduce the power consumption even if the error occurs in SNR estimation.
4. Simulation results
To evaluate the effectiveness of the proposed algorithm, simulations were conducted for mobile communication standards such as CMMB [16] and DVBS2 [17]. The simulation results for CMMB are summarized in Table 1. The experimental results show that power consumption and the amount of computation required are effectively reduced when the SNR is less than 6. Also, we verified that there was no BER performance degradation when we applied the proposed algorithm.
DVBS2 supports various code rates, and decoding is carried out by selecting an appropriate code rate according to the SNR value. Figure 8 shows BER versus SNR curves when the Hmatrix of DVBS2 is short in length. From these figures, we observe that as SNR values increase, and performance degradation becomes minimal even if we increase the code rates if the ACM technique was applied. Therefore, in DVBS2, decoding is processed by selecting an appropriate code rate depending on the SNR value.
Figure 9 shows the average iteration counts for various code rates versus SNR values. It is clearly observed that the iteration counts change as code rate and SNR values. We apply the proposed adaptive parity check algorithm by selecting the best code rate for each SNR value. The best code rates for each SNR value were drawn from results of simulations and previously published reports [18].
Table 2 summarizes the iteration counts when the block length is short in DVBS2 standard. Table entries in bold and italic fonts are the selected best code rates for specific SNR values. For example, when SNR is a value between 0.5 and 1, the best code rate is 2/5. When SNR falls between 1.5 and 2, the best code rate is 3/5.
When we use our novel proposed algorithm, we can select a code rate of 3/5 when the SNR is 2.7, and the average iteration count will be 23.62. However, since the minimum iteration count will be 19 in this case, we may skip the parity check and tentative checking operations up to the 19th iteration without affecting performance.
By running simulations, we verified that skipping the parity check and tentative check operations up to the minimum number of iterations does not affect performance. In addition, by skipping these operations, the total simulation time was reduced significantly. Table 3 shows the reduced simulation time after applying the proposed novel algorithm.
In the next section, we present experimental results on power consumption when we implement the proposed algorithm in hardware.
5. Implementation results
To evaluate the performance of our algorithm, we implemented a decoder for (3,6) regular LDPC codes, the length of which is 9216 (CMMB code rate = 1/2 code). As shown in Figure 10, we implemented the proposed decoder, which has a partially parallel architecture [19].
To implement the proposed adaptive paritycheck architecture, lookup tables were used both to indicate whether we should carry out parity check and to adjust the coefficients of the Modified MinSum algorithm.
The proposed LDPC decoder architecture was synthesized by Synopsys's Design Compiler using the Chartered 0.18 μm CMOS cell library. The size of the implemented decoder is 256 K (in NAND2) (Table 4).
We measured the power consumption of the synthesized design using Synopsys's Power Compiler. Figure 11 shows the amount of power consumption for each operation when a decoding iteration is carried out. A tentative operation simply stores the decision value in a buffer using the results from bit node operation. Thus, the amount of power consumption is not significant. However, the paritycheck operation first reads values from the buffer using addresses generated by AGU, and then carries out parity checking, where the amount of power consumption is significant. The amount of power consumption overhead due to the addition of the comparison unit between SNR values and LUTs to implement the proposed algorithm is negligible (less than 0.1% of the total power consumption). The amount of power consumed by the SNR estimator is not measured, since the SNR estimation unit is included in every ACMbased DVBS2 and CMMB decoding. Therefore, it should not be regarded as an additional overhead in the proposed approach.
As shown in Figure 12, the smaller the SNR is, the greater number of iterations the decoding requires. It is obvious that repeated computation of the paritycheck equation and the tentative decision will lead to high latency and power consumption. If we compute these functions only if the SNR estimation falls within a certain range, then we can avoid excessive power consumption due to unnecessary parity checks and tentative decisions.
For example, according to Table 1 the average number of iterations is 7.75 when the SNR is 2.5 dB. Up to the fourth iteration, we may omit paritycheck and tentative operations since we have no performance degradation. When we perform paritycheck and tentative operations at every iteration, the amount of power consumption is 256.63 mW. When we skip paritycheck and tentative operations until the fourth iteration, the amount of power consumption becomes 235.43 mW. Therefore, the amount of power consumption is reduced by 21.10 mW. We also observe that there is a significant reduction in power consumption for the SNR range of 26 dB. Especially, approximately 10% of power consumption is reduced for the SNR range of 1.52.5 dB.
Next, we discuss the effectiveness of the proposed algorithm for reducing the power consumption for DVBS2. We implemented DVBS2 in hardware as described in [20, 21]. Figure 13 shows the reduction of power consumption after the novel algorithm is applied. As shown in Figure 14, the effectiveness of power reduction for DVBS2 at various data rates is very good, even at high SNR values.
6. Conclusion
In this article, we propose a novel adaptive paritycheck decoding scheme based on SNR estimation. Our proposed scheme does not require any additional hardware. We observe that the iteration count until the completion of LDPC decoding can be predicted by the SNR value. Therefore, we may omit computation of the parity check and the tentative decision if the SNR value is too low to lead to successful decoding, which, in turn, reduces power consumption. Experimental results show that significant amounts of power reduction may be realized when SNR values are low. We expect that by applying this algorithm to the design of mobile devices with digital broadcasting chips, we can increase their battery life considerably.
Algorithm 1. LLR decoding algorithm
1: {Initialization :}
Set iteration number.i = 0., and F_{ n } (LLR) for bit nodes (n = 1,2,...,N)
and for each (m, n) if H_{ mn } = 1 set Z_{ mn } = F_{ n } (1)
2: while i ≤ i_{max}
3: for all (the check node) do
where each set (m,n) if H_{ mn } = 1
4: end for
5: for all (the bit node) do
where each set (m,n) if H_{ nm } = 1 Update
6: end for
7: for all for (n = 1,2,...,N) Compute all the tentatives do
8: end for
9: for all for (n = 1,2,...,N) Parity Check do
10: end for
11: end while
Algorithm 2. Using adaptive parity check for modified UMPBP
1: {Initialization :}
Set iteration number i = 0, and F_{ n } (LLR) for bit nodes (n = 1,2,...,N)
and for each (m,n) if H_{ mn } = 1 set Z_{ mn } = F_{ n } (10)
2: while i ≤ i_{max}
3: for all (the check node) do
where each set (m, n) if H_{ mn } = 1
4: end for
5: for all (the bit node) do
where each set (m, n) if H_{ mn } = 1 Update
6: end for
7: if (i > SNR Estimation_Table)
8: for all for (n = 1,2,...,N) Compute all the tentative do
9: end for
10: for all for (n = 1,2,...,N) Parity Check do
11: end for
12: end if
13: else if
continue i+
14: end if
15: end while
Abbreviations
 ACM:

adaptive coding and modulation
 LDPC:

low density parity check
 MCS:

modulation and coding scheme
 ML:

maximum likelihood
 MSE:

mean square error
 SNV:

signaltonoise variance
 SOF:

start of frame.
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Acknowledgements
"This research was supported by the MKE(The Ministry of Knowledge Economy), Korea, under the ITRC(Information Technology Research Center) support program supervised by the NIPA(National IT Industry Promotion Agency)" (NIPA2011C109011000010)
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Park, JY., Chung, KS. An adaptive lowpower LDPC decoder using SNR estimation. J Wireless Com Network 2011, 48 (2011). https://doi.org/10.1186/16871499201148
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DOI: https://doi.org/10.1186/16871499201148
Keywords
 LDPC
 decoder
 SNR estimation
 low power