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Nonvolatile memory reduction based on 1D memory space mapping of a specific set of QCLDPC codes
EURASIP Journal on Wireless Communications and Networking volumeÂ 2012, ArticleÂ number:Â 191 (2012)
Abstract
Supporting a great diversity of multirate Hmatrices for multiple communication protocols requires a large amount of nonvolatile memory, which may consume a large silicon area or logic elements and constrain the implementation of an overall decoder. Therefore, schemes for memory reduction are necessary to make the paritycheck storage more compact. This study proposes a specific set of quasicyclic lowdensity paritycheck (LDPC) (QCLDPC) codes which can transfer a traditional twodimensional (2D) paritycheck matrix (Hmatrix) into a onedimensional (1D) memory space. Compared to the existing schemes, the proposed codes and memory reduction scheme do achieve significant reduction rates. Within a fixed memory space, many more Hmatrices for diverse communication protocols can be saved via the proposed QCLDPC codes, which are well constructed from modified WelchCostas sequences. Furthermore, relatively good error performances, which outperform computergenerated random LDPC codes and SridharaFujaTanner codes, are also shown in our simulation results. Consequently, we conclude that the proposed QCLDPC codes can enlarge the capacity for saving much more lowBER (bit error rate) Hmatrices within a fixed memory space.
1. Introduction
Lowdensity paritycheck (LDPC) codes were first introduced by Gallager in 1962, but they were rarely used since implementing them in hardware was impractical in the 1960s. The value of LDPC codes was rediscovered by Mackay and Neal in 1996 [1]. Since then, LDPC codes have gained a lot of attention due to their excellent error correction capability. A binary (j, k)regular LDPC code is defined as the null space of a sparse paritycheck matrix H over GF(2) and satisfies the following properties: (1) each column has weight j; (2) each row has weight k; (3) no two rows (or two columns) have more than one 1component in common; (4) both j and k are much smaller than the code length.
Most methods for designing good LDPC codes are based on random constructions, but the lack of structure makes the encoding process complicated. Furthermore, the nonvolatile memory required to store the paritycheck matrices may be prohibitive in practical applications.
Nowadays, some wireless devices are designed to be both tiny and capable of supporting multiple communication functions, such as WLAN [2, 3], 3G, DVBS2 [4], CMMB [5], etc. Therefore, a great diversity of LDPC codes is employed for the demand of error corrections. Compared to overall decoders, the storage for multiple LDPC Hmatrices is very area consuming. Therefore, memory reduction schemes are necessary for reducing the memory requirements as much as possible. quasicyclic LDPC (QCLDPC) codes are always employed for this purpose since even trivial approaches can achieve huge gains in memory reduction.
There are two primary types of paritycheck matrices of LDPC codes: the pseudorandom matrix [6] and the quasicyclic matrix [7, 8]. The latter, whose encoding complexity is directly proportional to the code length, is widely applied in consumer electronics. Several classes of QCLDPC codes [8â€“10] have been proposed. Such codes can achieve good error performance comparable with computergenerated random LDPC codes. However, in terms of implementation aspects, QCLDPC codes for multirate communication sessions and diverse communication protocols need to be stored concurrently. As indicated in [6], directly employing the lookup tables for saving multiple Hmatrices is always prohibitive.
The motivation of this study is to propose a specific set of QCLDPC codes with extremely low memory requirements. To achieve this goal, we introduce properly constructed QCLDPC codes which can be classified as a specific set of formerly proposed modified WelchCostas (MWCOCS) codes [11]. These LDPC codes are constructed by multilevel sequences [8, 12, 13] with the property that any two different rows have at most one element in common. Based on our proposed 2D to 1D memory space mapping, each code in the specific set can achieve a huge reduction rate due to its particular structure.
Some studies related to H_{ROM} storage are shown in Table 1, in which critical implementation issues for LDPC codes are presented:

(1)
As indicated in [14], the unreduced H_{ROM} is definitely areaconsuming. In fact, it may occupy 60% area of the overall decoder. Therefore, reduction schemes are necessary for degrading the memory demand.

(2)
The reduction impact is still unobvious in some LDPC codes with irregular structures. Possible approaches have been applied in [15].

(3)
From [5], some code structures can massively be reduced to merely 8.5% of the overall area. This achievement is meaningful, especially when the target device is specified. For example, after optimization, this decoder can easily fit an ALTERA EP2S15F484C3 FPGA (250 K gates), and hence the search for a larger or more expensive device is no longer necessary.

(4)
The study [2] indicates that supporting multiple Hmatrices will increase the memory demand. Although the required nonvolatile memory has been optimized as a [324 Ã— 48] lowpower ROM (60 K gates), it still consumes a large portion of the hardware resource.
To address the critical issues mentioned above, we propose extremely compact codes to significantly reduce a single Hmatrix storage. Moreover, a reduction scheme via data mapping and the proposed codes are also demonstrated to further degrade the memory demand for multirate Hmatrices storage. Both of the proposed codes and the further reduction scheme can achieve huge reduction rates. Compared to existing approaches, this study can squeeze many more Hmatrices within a fixed memory space.
This article is organized as follows. In the introduction section, we highlighted the need for H_{ROM} reduction and clarify the motivation of our approach. In Section 2, we explain how a QCLDPC paritycheck matrix is characterized by merely storing the shift values of its identity submatrices for memory efficiency. Our similar codes with extremely low memory requirements for CMMB, WLAN, and WIMAX are introduced in Section 3. The proposed MWCOCS LDPC block codes and their 1D memory space mapping are introduced in Sections 4 and 5. In Section 6, a design example demonstrates how multirate Hmatrices storage can be further reduced. For a tiny device designed to support more Hmatrices for diverse communication protocols, this example should not be considered negligible. Finally, we offer conclusions in Section 7.
2. QCLDPC block codes storage
For QCLDPC codes, storing H [2] involves saving the shift values of identity submatrices and their column positions. The column positions can easily be generated by an address generator unit (AGU) [5]. As for the storage of shift values, it requires a 2D matrix which can only be carried out by a nonvolatile memory space. Nonvolatile memory severely consumes the logic elements. Properly constructed LDPC codes require less nonvolatile memory and can make the hardware resource available for decoder improvements or more Hmatrices storage.
The content stored in the nonvolatile memory is used for generating actual addresses which point to soft messages stored in the volatile memory (RAM). An actual address can easily be determined by adding an offset address to the base address. A decoder retrieves a soft message by accessing the RAM via an actual memory address. The number of addresses required to retrieve all the content of message RAM equals to the number of 1components in the Hmatrix. Each 1component in H represents a RAM address. All the RAM addresses needed for the decoder to obtain the soft messages are stored in the nonvolatile memory. Without optimization, the size of this nonvolatile memory is equal to Z Ã— U bits, where Z is the address width (Z â‰§ log_{2}N) [5], and U is the total number of 1components in an Hmatrix with code length N. In QCLDPC block codes, the nonvolatile memory for recording the RAM addresses can be replaced by a reduced 2D Ymatrix, in which only shift values are stored. With the content of Y and an AGU [5], the original memory space can effectively be reduced. This section shows how an Hmatrix of a QCLDPC code can be compactly stored and how actual addresses can be determined by an AGU.
2.1. Nonzero elements in hardware implementation
In terms of hardware implementations, the position of '1' in the same column of a paritycheck matrix actually represents an offset address. An actual address, which points to a soft message stored in the volatile memory, can be generated by the addition of an offset address and a base address. For an Nbit codeword, the offset addresses range between 0 and N  1. The actual addresses can be generated on the fly by an AGU which spans all the required memory addresses for message retrieval. The AGU requires only a small amount of data which characterizes the feature of H. This required data varies with different code structures. Chose the smallest integer Z (Z â‰§ log_{2}N), then each nonzero element in the H actually denotes to a Zbit offset address which can be used to retrieve a soft message stored in the corresponding message memory.
2.2. Message address determination
In Figure 1, a (3, 4)regular QCLDPC code is composed of 12 p Ã— p (p = 3) submatrices and can be expressed as a (12, 3, 4) QCLDPC code with codeword length N = 12. An offset address represented by 1_{r, v}is located at the r th (0 â‰¤ r â‰¤ jp1) row of the parity check Hmatrix and v th (0 â‰¤ v â‰¤ k1) column in which k circulant permutation submatrices are placed. A submatrix located at the u th row and v th column is cyclically shifted by y_{ u, v } positions, where y_{ u, v } can be represented by an u Ã— v (0 â‰¤ u â‰¤ j1) matrix as shown in Figure 2.
The offset address represented by 1_{ r, v }is determined as follows:
where c = r mod p. For example, 1_{0,1} and 1_{5,3} in Figure 1 are determined by
As a result, an offset address can easily be determined by a simple logic as shown in Figure 3. In (1), the comparison result of (y_{ u, v } + c) < p is obtained from a borrow bit. An accumulator of p, instead of a multiplier, can be employed to determine pv as the governing scanning operation accesses addresses in a specific order, and the parameter c is obtained by a modulop counter instead of a divider. All the parameters in (1) have sizes of less than Z bits. Therefore, the QCLDPC block codes can be characterized by a 2D matrix [5] Y (Y = y_{ u, v }) in which each element is a zbit (z â‰§ log_{2}p) data representing a shift value in the corresponding identity submatrix.
3. Reduction factors in recent memory reduction works
This section surveys recent studies related to the compact storage of a paritycheck Hmatrix. As shown in Table 2, the achievements of these studies are evaluated by the reduction factor with respect to the requirements of memory bits. An LDPC code is represented by its sparse paritycheck matrix of size M Ã— N and of density [16] defined as N_{ e }/(M Ã— N) [17] (N_{ e } is the number of ones in the Hmatrix and M is equal to NK). A direct representation of H exploits its sparseness to record only the nonzero column elements in each row or the nonzero row elements in each column. Hence, N Ã— j [18] elements or M Ã— k [5] elements need to be recorded. The LDPC codes designed for the China Mobile Multimedia Broadcasting (CMMB) [5] system are cyclicshifted with 36 bits every R_{ p } row (R_{ p } = 18 in rate = 1/2 and R_{ p } = 9 in rate = 3/4) and the required memory to store all the nonzero elements is M Ã— k Ã— Z (Z â‰§ log_{2}N) bits without applying an AGU. With an AGU, the feature of H is abstracted by two matrices (H 'matrix and Imatrix) which generate the actual addresses on the fly. The other memory reduction methods employ only one reduced matrix. These methods are compared with each other by a reduction factor with reference to M Ã— k Ã— Z. As shown in Table 2, the memory requirements, reduction factors, and application examples of these methods are available.
Due to the limitation of choosing p (p is a prime), we are not able to exactly construct the same codes with the existing approaches. However, to make relatively fair comparisons, some similar codes are constructed to exploit the memory efficiency of the proposed MWCOCS LDPC codes. The similar codes are defined as the codes which have similar code lengths, the same code rates, and the same weight k as the compared codes. In terms of the requirement of memory bits shown in Table 3, the stateoftheart work [5] for CMMB reduced the Hmatrices (rate = 0.5, 0.75) to merely 1728 bits. In our similar codes, 88 and 140 bits are required, respectively, for the described CMMB tworate Hmatrices. Since these two matrices can be merged into one, 140 bits are required by our similar codes, and hence a 92% (1588/1728) reduction rate is achieved. Furthermore, compared to [2], our similar codes (rate = 0.5) for WLAN and WMAX also achieve a reduction rate of 88%.
Table 3 and Figure 4 also show the synthesis results of our similar codes (synthesized by Synplify Pro 7.2). The code storage (including the cost of addressing the memories and the cost of routing the data) of our similar codes for CMMB require 30 gates, 0.4% of 7 k gates required in [5]. The gain (99.6%) evaluated by the gate count is even larger than the gain (92%) estimated by memory bits. This difference is attributed to the fact that cost of addressing a more compact memory space is much simpler. We also synthesized our similar codes for WLAN and WMAX, the synthesis results show merely 71 and 83 gates are required, respectively. As for this part, the gate count consumed by a rate = 0.5 Hmatrix is not available in [2].
Compared to the existing approaches, many more Hmatrices constructed by our approach for diverse communication protocols can be supported within a fixed nonvolatile memory space. The extremely low memory requirements of the proposed codes are achieved by a 2D to 1D memory space mapping. Consequently, the j Ã— k Ã— Z bits required by a traditional 2D storage for QCLDPC codes can be reduced to (j + k1) Ã— z bits, where z is the smallest integer satisfying z â‰¥ log_{2}p.
4. Methods to Construct memoryefficient MWCOCS LDPC codes
A cycle in a Tanner graph is a sequence of connected vertices that starts and ends at the same vertex in the graph, and which contains other vertices no more than once. To upgrade the performance of LDPC codes, it is necessary to avoid 4cycles, which is the shortest possible length for a Tanner graph. The girth of an LDPC code is the length of the smallest cycle. Since cycles of short length may degrade the performance of LDPC codes, it is necessary to ensure that the Tanner graph of the LDPC codes is free of cycles with lengths of 4 and hence have girths of at least 6 [13]. In Section 4.1, we introduce how to construct the proposed memoryefficient QCLDPC codes and prove that no 4cycles are present. The construction examples and the simulation results are shown at the last two subsections.
4.1. Construction procedure
In this section, we propose a method for constructing the QCLDPC codes with memory reduction. For clarity of exposition, the MWCOCS LDPC codes [11] are used as an exemplification. However, for the application of the proposed memoryefficient scheme, only the cyclic parts of the MWC sequences are adopted in the construction procedure.
An element from GF(p) in a j Ã— k preliminary matrix Y can be represented as y_{ u, v }, where the (u, v)th element of Y can be calculated by Equation (2) with the corresponding values of a_{ u } and b_{ v }, for fixed parameters Ï† and Î±.
where 0 â‰¤ u â‰¤ j1, 0 â‰¤ v â‰¤ k1.
For memory efficiency, two specific sequences {a_{0}, a_{1},..., a_{j1}} and {b_{0}, b_{1},..., b_{k1}} are constructed by the following procedure.
First, choose basic parameters j, k, and p (p is a prime) where the j, k âˆˆ integer.
Second, choose initial values a_{0}, b_{0}, and grid size f where 0 â‰¤ a_{ m } (= a_{0} + mf) â‰¤ p2 for m = 0, 1,..., j1, 1 â‰¤ b_{ n } (= b_{0} + nf) â‰¤ p1 for n = 0, 1,..., k1, and f âˆˆ {1, 2,..., p1}.
Third, substitute a_{ m } = a_{0} + mf and b_{ n } = b_{0} + nf into (2). Note that a_{ i } â‰ a_{ j } and b_{ i } â‰ b_{ j } if i â‰ j. where Î± âˆˆ {1, 2,..., p1}, Ï† âˆˆ {0, 1,..., p1}, and Î² is the primitive element of GF(p). Then the following equation is obtained:
The proposed parity check matrix H, which reduces the nonvolatile memory demand, can be represented by a j Ã— k array of circulant permutation submatrices shown as follows:
where I(x) is a p Ã— p identity submatrix with rows cyclically shifted to the right by x positions. For example, I(1) is the following permutation matrix:
Hence, the resulting H, which has j ones in each column and k ones in each row, represents a (j, k)regular LDPC code (this LDPC code is also an [N, K] regular LDPC code, where N (= kp) is the block length of the MWCOCS LDPC code and K is the number of message bits).
The size of the paritycheck matrix H is jp Ã— kp. Due to the linear dependence among the rows of H, it has a code rate of r = K/N â‰¥ 1(j/k). Actually, since the summation of the p rows of the J th submatrices [I(y_{J,0}) I(y_{J,1})...I(y_{J, k1})] (0 â‰¤ J â‰¤ j1) in (4) are equal to an all1 vector, there are at least j1 dependent rows in H. Therefore, the Tanner graph of the resulting LDPC codes is free of cycles with lengths of 4 and hence has a girth of at least 6.
Based on (3), if two sequences a_{ m } and b_{ n } are both ordered incrementally or decrementally by f, an element y_{s, t}will be equal to y_{m, n}, as s + t is equal to m + n in the preliminary matrix Y. In (6), we also verify that if a_{ m } and b_{ n } are ordered in an opposite direction to each other, an element y_{s, t}is still equal to y_{m, n}when st = mn. Note that m â‰ s, n â‰ t.
4.2. Construction examples
According to (3) and (6), two construction examples are shown as follows. The initial values chosen for the required sequences can be different.
Example A: A [155, 64] MWCOCS LDPC code (p = 31)
Let j = 3, k = 5, f = 3. We select {a_{0}, a_{1}, a_{2}} = {0, 3, 6} and {b_{0}, b_{1}, b_{2}, b_{3}, b_{4}} = {1, 4, 7, 10, 13}. By using (3) and (4) with fixed parameter Î± = 1, Ï† = 0, we can form the following paritycheck matrix:
In Example A, two sequences are both ordered increasingly, and the resulting Hmatrix shows the same shift values in the identity submatrices from the lower left to the upper right.
Example B: We select {a_{0}, a_{1}, a_{2}} = {0, 3, 6} and {b_{0}, b_{1}, b_{2}, b_{3}, b_{4}} = {13, 10, 7, 4, 1}, and then the following paritycheck matrix is formed:
Example B shows that a memoryefficient LDPC codes also can be constructed by two sequences ordered in the opposite direction of each other. The Hmatrix is constructed by a_{ m } = {a_{0}, a_{0}+f, a_{0}+2f,..., a_{0}+(j1)f} and b_{ n } = {b_{0}, b_{0}f, b_{0}2f,..., b_{0}(k 1)f}. The resulting Hmatrix shows the same shift values in the identity submatrices from the upper left to the lower right. Each resulting Hmatrix shown in Examples A and B is a 93 Ã— 155 matrix and describes a (3, 5)regular LDPC code with rate = 64/155 â‰ˆ 0.4129 (by using Gaussian elimination, we know that H has a rank of 91).
5. 2D to 1D mapping and simulation results of memoryefficient MWCOCS LDPC codes
Due to the memoryefficient property mentioned in Section 4, the corresponding paritycheck H matrices of the proposed MWCOCS LDPC block exploit superior regularity. This regular code structure enables a mapping of a 2D matrix into a compact 1D memory space. As shown in Figure 5, the Hmatrix in Example A is mapped from a 2D y_{ u, v } matrix into a 1D memory space y_{ w }. As a result, the required memory can be reduced from j Ã— k Ã— z bits to (j + k1) Ã— z bits, where w = u + v. The Hmatrix in Example B is constructed by two sequences ordered in opposite directions of each other. In memory indices transformations, as shown in Figure 6, a 2D y_{ u, v } matrix in Example B is mapped into a 1D memory space y_{ w }, where w = v  u + (j1). No doubt, these two Hmatrices in Examples A and B exhibit the same memoryefficient feature. Therefore, the construction of memoryefficient MWCOCS LDPC block codes can be conducted as follows:
We construct two specific sequences {a_{0}, a_{1},..., a_{j1}} and {b_{0}, b_{1},..., b_{k1}}, which satisfy the conditions that 0 â‰¤ a_{ m } (= a_{0} Â± mf) â‰¤ p2 for m = 0, 1,..., j1, 1 â‰¤ b_{ n } (= b_{0} Â± nf) â‰¤ p1 for n = 0, 1,..., k1, f âˆˆ{1, 2,..., p1} and p is an odd prime. Note that a_{ i } â‰ a_{ j } and b_{ i } â‰ b_{ j } if i â‰ j. Then the following two cases are able to construct memoryefficient MWCOCS LDPC codes, which can be mapped from 2D Hmatrices into 1D memory spaces.
Case A: Two sequences are ordered in the same direction, then the 2D matrix y_{ u, v } is mapped into a 1D memory space y_{ w }, where w = u + v.
Case B: Two sequences are ordered in opposite directions of each other, and then the 2D matrix y_{ u, v } is mapped into a 1D memory space y_{ w }, where w = v  u + (j  1).
In addition to the memoryefficient feature, the proposed codes are also required to provide good error performance. To show the simulation results of the error performances which can be achieved by the memoryefficient MWCOCS LDPC codes, the bit error rates of the proposed codes and the competitive codes are compared via a binary phaseshift keyingmodulated additive white Gaussian noise channel with signaltonoise ratio E_{ b }/N_{0}. In all cases, the iterative sumproduct algorithm was used for decoding. The proposed (3, 5)regular memoryefficient MWCOCS LDPC code in Figure 7 is not as good as the randomly constructed LDPC codes. It shows an error floor which may be caused by their limited minimum distance (for a (j, k)regular QCLDPC code, the minimum distance is at most (j+1)! [19]). This performance loss may be attributed to the fact that we have introduced various constraints on the set of code parameters, which influence the performance of belief propagation decoding. To resolve this problem, several memoryefficient MWCOCS LPDC codes with columnweight 4 are constructed. As shown in Figure 8, the memoryefficient MWCOCS LDPC codes perform slightly better than the randomly constructed LDPC codes and SridharaFujaTanner (SFT) codes [7]. Figure 9 depicts the performance of highrate LDPC codes with different constructions. The performances of rate = 0.75, (4, 16)regular LDPC codes with two different block lengths N = 1648 and N = 4016 are shown. It can be seen that the proposed memoryefficient MWCOCS LDPC codes outperform the competitive codes under similar code rates and moderate block lengths.
6. A further reduction for multirate Hmatrices storage
In this section, a design example is demonstrated to show how a further reduction can be achieved after 1D memory space mapping. As we have mentioned, all possible schemes for further reduction are meaningful as long as they can achieve significant gains, especially when the hardware resource is constrained and the demand for diverse Hmatrices increases.
Four diverse Hmatrices, which provide comparable error performances in Figures 8 and 9, are compactly saved by the proposed memory reduction scheme. In Figure 10, the four Hmatrices are represented by the shift values of the corresponding identity submatrices. For example, the element '27' represents an identity submatrix I(27) with its shift value parenthesized. The corresponding shift value for each identity submatrix is generated via Equation (3) using '3' as a primitive element.
6.1. Preprocess of the elements in 1D memory spaces
The memory requirement for four Hmatrices is reduced to 483 bits after 1D space mapping. To save several Hmatrices in multirate communications, a further reduction can be achieved by merging the same shift values with the same memory indices into one before synthesis. That is, except for the 1D memory space mapping mentioned in Section 5, if the overlapped elements in diverse Hmatrices can be preprocessed, a better optimization can be achieved in our synthesis result. In Figure 11, each Hmatrix has been mapped into a 1D memory space. We find that these 1D memory spaces have the same elements in specific memory indices. The required memory can be more compact after all the overlapped elements are merged into one.
6.2. Design architecture
The architecture of the design example is shown in Figure 12. An Hregister, employed for saving a specific Hmatrix selected from the four Hmatrices, prevents accessing of the nonvolatile memory frequently during the communication time. Therefore, the implementation can be divided into two parts, namely nonvolatile storage and volatile storage. In Figure 12, the nonvolatile part is implemented by sticking the inputs of the 4input multiplexer to logic high or logic low, instead of using a real ROM block. Before a session of communication commences, the input signal H_select selects a specific 1D memory space and loads its content into an Hregister. During communication, only the Hregister needs to be accessed to determine the message addresses, and the nonvolatile memory access is thus prevented. In a session of communication, all the shift values can be spanned through the content of the Hregister. As shown in Table 4, four diverse Hmatrices which provide relatively good error performances are included in the Hlibrary. Since only one Hmatrix is required for error correction in a specific session of communication, it is not necessary for all the four Hmatrices to be loaded once at a time.
6.3. Synthesis results
Before synthesizing the design example, by applying the proposed 2D to 1D memory space mapping scheme, the total nonvolatile memory demand is reduced to 483 bits, and the corresponding reduction factor is only 6.94 Ã— 10^{4}. A further optimization is achieved by a reduction factor of 5.02 Ã— 10^{4} after preprocessing the overlapped elements before synthesis. The synthesis report in the last line of Table 4 shows that addressing the memories and routing the data require 13 gates, 152 memoryless and gatefree output pads, and a 16DFF Hregister which spans all the shift values. The schematic view of the synthesis result is also shown in Figure 12. During a communication session, all the shift values of a specific H can be retrieved through the 152bit extended output pads. These pads send out fixed logic levels mixed with the output of the Hregister. Therefore, in a session of communication, only the 152bit (maximum size of the four 1D memory spaces) output data spanned by the Hregister is accessed for fast retrieval of the shift values. The nonvolatile part will not be accessed until a new session of communication using another Hmatrix begins.
7. Conclusion
Memoryefficient MWCOCS LDPC codes were proposed to reduce the nonvolatile memory demand for Hmatrix storage. The described similar codes outperform other recent approaches with huge memoryreduction rates. Compared to CMMB and WIMAX/WLAN, our similar codes have, respectively, achieved 92 and 88% reduction rates in terms of the requirement of memory bits. In the synthesis result of our similar code storage for CMMB, the gain (99.6%) evaluated by gate count is even larger than the gain (92%) estimated by memory bits. In addition, the proposed codes also show relatively good error performances comparable with competitive codes in columnweight 4 constructions. Furthermore, a design example was also synthesized to be every compact for multirate Hmatrices storage. In implementing wireless applications for multiple communication protocols within a fixed size of memory space, our approach is of good worth. As we have mentioned, even when the huge gain achieved is only a small fraction of the overall decoder, it cannot be considered negligible as the demand for diverse Hmatrices storage of multiple communication protocols increases. Especially, for a tiny device with a very limited size of memory space, applying the proposed approach can enhance the capability for supporting many more error correction functions.
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This research was partially supported by the National Science Council in Taiwan (Grant No.NSC982221E168004MY3).
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Young, CP., Chia, CC., Yang, CC. et al. Nonvolatile memory reduction based on 1D memory space mapping of a specific set of QCLDPC codes. J Wireless Com Network 2012, 191 (2012). https://doi.org/10.1186/168714992012191
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DOI: https://doi.org/10.1186/168714992012191