Non-volatile memory reduction based on 1-D memory space mapping of a specific set of QC-LDPC codes

Low-density parity-check (LDPC) codes were first introduced by Gallager in 1962, but they were rarely used since implementing them in hardware was impractical in the 1960s. The value of LDPC codes was rediscovered by Mackay and Neal in 1996 [1]. Since then, LDPC codes have gained a lot of attention due to their excellent error correction capability. A binary (j, k)-regular LDPC code is defined as the null space of a sparse parity-check matrix H over GF(2) and satisfies the following properties: (1) each column has weight j; (2) each row has weight k; (3) no two rows (or two columns) have more than one 1-component in common; (4) both j and k are much smaller than the code length.

Most methods for designing good LDPC codes are based on random constructions, but the lack of structure makes the encoding process complicated. Furthermore, the non-volatile memory required to store the parity-check matrices may be prohibitive in practical applications.

Nowadays, some wireless devices are designed to be both tiny and capable of supporting multiple communication functions, such as WLAN [2, 3], 3G, DVB-S2 [4], CMMB [5], etc. Therefore, a great diversity of LDPC codes is employed for the demand of error corrections. Compared to overall decoders, the storage for multiple LDPC H-matrices is very area consuming. Therefore, memory reduction schemes are necessary for reducing the memory requirements as much as possible. quasi-cyclic LDPC (QC-LDPC) codes are always employed for this purpose since even trivial approaches can achieve huge gains in memory reduction.

There are two primary types of parity-check matrices of LDPC codes: the pseudorandom matrix [6] and the quasi-cyclic matrix [7, 8]. The latter, whose encoding complexity is directly proportional to the code length, is widely applied in consumer electronics. Several classes of QC-LDPC codes [8–10] have been proposed. Such codes can achieve good error performance comparable with computer-generated random LDPC codes. However, in terms of implementation aspects, QC-LDPC codes for multi-rate communication sessions and diverse communication protocols need to be stored concurrently. As indicated in [6], directly employing the lookup tables for saving multiple H-matrices is always prohibitive.

The motivation of this study is to propose a specific set of QC-LDPC codes with extremely low memory requirements. To achieve this goal, we introduce properly constructed QC-LDPC codes which can be classified as a specific set of formerly proposed modified Welch-Costas (MWC-OCS) codes [11]. These LDPC codes are constructed by multilevel sequences [8, 12, 13] with the property that any two different rows have at most one element in common. Based on our proposed 2-D to 1-D memory space mapping, each code in the specific set can achieve a huge reduction rate due to its particular structure.

To address the critical issues mentioned above, we propose extremely compact codes to significantly reduce a single H-matrix storage. Moreover, a reduction scheme via data mapping and the proposed codes are also demonstrated to further degrade the memory demand for multi-rate H-matrices storage. Both of the proposed codes and the further reduction scheme can achieve huge reduction rates. Compared to existing approaches, this study can squeeze many more H-matrices within a fixed memory space.

This article is organized as follows. In the introduction section, we highlighted the need for H_ROM reduction and clarify the motivation of our approach. In Section 2, we explain how a QC-LDPC parity-check matrix is characterized by merely storing the shift values of its identity sub-matrices for memory efficiency. Our similar codes with extremely low memory requirements for CMMB, WLAN, and WIMAX are introduced in Section 3. The proposed MWC-OCS LDPC block codes and their 1-D memory space mapping are introduced in Sections 4 and 5. In Section 6, a design example demonstrates how multi-rate H-matrices storage can be further reduced. For a tiny device designed to support more H-matrices for diverse communication protocols, this example should not be considered negligible. Finally, we offer conclusions in Section 7.

For QC-LDPC codes, storing H [2] involves saving the shift values of identity sub-matrices and their column positions. The column positions can easily be generated by an address generator unit (AGU) [5]. As for the storage of shift values, it requires a 2-D matrix which can only be carried out by a non-volatile memory space. Non-volatile memory severely consumes the logic elements. Properly constructed LDPC codes require less non-volatile memory and can make the hardware resource available for decoder improvements or more H-matrices storage.

The content stored in the non-volatile memory is used for generating actual addresses which point to soft messages stored in the volatile memory (RAM). An actual address can easily be determined by adding an offset address to the base address. A decoder retrieves a soft message by accessing the RAM via an actual memory address. The number of addresses required to retrieve all the content of message RAM equals to the number of 1-components in the H-matrix. Each 1-component in H represents a RAM address. All the RAM addresses needed for the decoder to obtain the soft messages are stored in the non-volatile memory. Without optimization, the size of this non-volatile memory is equal to Z × U bits, where Z is the address width (Z ≧ log₂N) [5], and U is the total number of 1-components in an H-matrix with code length N. In QC-LDPC block codes, the non-volatile memory for recording the RAM addresses can be replaced by a reduced 2-D Y-matrix, in which only shift values are stored. With the content of Y and an AGU [5], the original memory space can effectively be reduced. This section shows how an H-matrix of a QC-LDPC code can be compactly stored and how actual addresses can be determined by an AGU.

2.2. Message address determination

In Figure 1, a (3, 4)-regular QC-LDPC code is composed of 12 p × p (p = 3) sub-matrices and can be expressed as a (12, 3, 4) QC-LDPC code with codeword length N = 12. An offset address represented by 1_{r, v}is located at the r th (0 ≤ r ≤ jp-1) row of the parity check H-matrix and v th (0 ≤ v ≤ k-1) column in which k circulant permutation sub-matrices are placed. A sub-matrix located at the u th row and v th column is cyclically shifted by y _{u, v} positions, where y _{u, v} can be represented by an u × v (0 ≤ u ≤ j-1) matrix as shown in Figure 2.

The offset address represented by 1 _{r, v} is determined as follows:

$\begin{array}{ll}if\hfill & \left({\mathit{y}}_{\mathit{u}\mathbf{,}\mathit{v}}+c\right)<p\hfill \\ 1_{r,v}=\left({\mathit{y}}_{\mathit{u}\mathbf{,}\mathit{v}}+c\right)+pv;\hfill \\ else\hfill \\ 1_{r,v}=\left({\mathit{y}}_{\mathit{u}\mathbf{,}\mathit{v}}+c\right)-p+pv;\hfill \end{array}$

(1)

where c = r mod p. For example, 1_0,1 and 1_5,3 in Figure 1 are determined by

$1_{0,1}=\left({\mathit{y}}_{\mathbf{0},\mathbf{1}}+0\right)+3\times 1=4.$

$1_{5,3}=\left({\mathit{y}}_{\mathbf{1},\mathbf{3}}+2\right)-3+3\times 3=9.$

As a result, an offset address can easily be determined by a simple logic as shown in Figure 3. In (1), the comparison result of (y _{u, v} + c) < p is obtained from a borrow bit. An accumulator of p, instead of a multiplier, can be employed to determine pv as the governing scanning operation accesses addresses in a specific order, and the parameter c is obtained by a modulo-p counter instead of a divider. All the parameters in (1) have sizes of less than Z bits. Therefore, the QC-LDPC block codes can be characterized by a 2-D matrix [5] Y (Y = y _{u, v} ) in which each element is a z-bit (z ≧ log₂p) data representing a shift value in the corresponding identity sub-matrix.

Table 3 and Figure 4 also show the synthesis results of our similar codes (synthesized by Synplify Pro 7.2). The code storage (including the cost of addressing the memories and the cost of routing the data) of our similar codes for CMMB require 30 gates, 0.4% of 7 k gates required in [5]. The gain (99.6%) evaluated by the gate count is even larger than the gain (92%) estimated by memory bits. This difference is attributed to the fact that cost of addressing a more compact memory space is much simpler. We also synthesized our similar codes for WLAN and WMAX, the synthesis results show merely 71 and 83 gates are required, respectively. As for this part, the gate count consumed by a rate = 0.5 H-matrix is not available in [2].

Compared to the existing approaches, many more H-matrices constructed by our approach for diverse communication protocols can be supported within a fixed non-volatile memory space. The extremely low memory requirements of the proposed codes are achieved by a 2-D to 1-D memory space mapping. Consequently, the j × k × Z bits required by a traditional 2-D storage for QC-LDPC codes can be reduced to (j + k-1) × z bits, where z is the smallest integer satisfying z ≥ log₂p.

A cycle in a Tanner graph is a sequence of connected vertices that starts and ends at the same vertex in the graph, and which contains other vertices no more than once. To upgrade the performance of LDPC codes, it is necessary to avoid 4-cycles, which is the shortest possible length for a Tanner graph. The girth of an LDPC code is the length of the smallest cycle. Since cycles of short length may degrade the performance of LDPC codes, it is necessary to ensure that the Tanner graph of the LDPC codes is free of cycles with lengths of 4 and hence have girths of at least 6 [13]. In Section 4.1, we introduce how to construct the proposed memory-efficient QC-LDPC codes and prove that no 4-cycles are present. The construction examples and the simulation results are shown at the last two subsections.

Due to the memory-efficient property mentioned in Section 4, the corresponding parity-check H matrices of the proposed MWC-OCS LDPC block exploit superior regularity. This regular code structure enables a mapping of a 2-D matrix into a compact 1-D memory space. As shown in Figure 5, the H-matrix in Example A is mapped from a 2-D y _{u, v} matrix into a 1-D memory space y _w . As a result, the required memory can be reduced from j × k × z bits to (j + k-1) × z bits, where w = u + v. The H-matrix in Example B is constructed by two sequences ordered in opposite directions of each other. In memory indices transformations, as shown in Figure 6, a 2-D y _{u, v} matrix in Example B is mapped into a 1-D memory space y _w , where w = v - u + (j-1). No doubt, these two H-matrices in Examples A and B exhibit the same memory-efficient feature. Therefore, the construction of memory-efficient MWC-OCS LDPC block codes can be conducted as follows:

We construct two specific sequences {a₀, a₁,..., a_j-1} and {b₀, b₁,..., b_k-1}, which satisfy the conditions that 0 ≤ a _m (= a₀ ± mf) ≤ p-2 for m = 0, 1,..., j-1, 1 ≤ b _n (= b₀ ± nf) ≤ p-1 for n = 0, 1,..., k-1, f ∈{1, 2,..., p-1} and p is an odd prime. Note that a _i ≠ a _j and b _i ≠ b _j if i ≠ j. Then the following two cases are able to construct memory-efficient MWC-OCS LDPC codes, which can be mapped from 2-D H-matrices into 1-D memory spaces.

Case A: Two sequences are ordered in the same direction, then the 2-D matrix y _{u, v} is mapped into a 1-D memory space y _w , where w = u + v.

Case B: Two sequences are ordered in opposite directions of each other, and then the 2-D matrix y _{u, v} is mapped into a 1-D memory space y _w , where w = v - u + (j - 1).

In addition to the memory-efficient feature, the proposed codes are also required to provide good error performance. To show the simulation results of the error performances which can be achieved by the memory-efficient MWC-OCS LDPC codes, the bit error rates of the proposed codes and the competitive codes are compared via a binary phase-shift keying-modulated additive white Gaussian noise channel with signal-to-noise ratio E _b /N₀. In all cases, the iterative sum-product algorithm was used for decoding. The proposed (3, 5)-regular memory-efficient MWC-OCS LDPC code in Figure 7 is not as good as the randomly constructed LDPC codes. It shows an error floor which may be caused by their limited minimum distance (for a (j, k)-regular QC-LDPC code, the minimum distance is at most (j+1)! [19]). This performance loss may be attributed to the fact that we have introduced various constraints on the set of code parameters, which influence the performance of belief propagation decoding. To resolve this problem, several memory-efficient MWC-OCS LPDC codes with column-weight 4 are constructed. As shown in Figure 8, the memory-efficient MWC-OCS LDPC codes perform slightly better than the randomly constructed LDPC codes and Sridhara-Fuja-Tanner (SFT) codes [7]. Figure 9 depicts the performance of high-rate LDPC codes with different constructions. The performances of rate = 0.75, (4, 16)-regular LDPC codes with two different block lengths N = 1648 and N = 4016 are shown. It can be seen that the proposed memory-efficient MWC-OCS LDPC codes outperform the competitive codes under similar code rates and moderate block lengths.

In this section, a design example is demonstrated to show how a further reduction can be achieved after 1-D memory space mapping. As we have mentioned, all possible schemes for further reduction are meaningful as long as they can achieve significant gains, especially when the hardware resource is constrained and the demand for diverse H-matrices increases.

Four diverse H-matrices, which provide comparable error performances in Figures 8 and 9, are compactly saved by the proposed memory reduction scheme. In Figure 10, the four H-matrices are represented by the shift values of the corresponding identity sub-matrices. For example, the element '27' represents an identity sub-matrix I(27) with its shift value parenthesized. The corresponding shift value for each identity sub-matrix is generated via Equation (3) using '3' as a primitive element.

6.1. Preprocess of the elements in 1-D memory spaces

The memory requirement for four H-matrices is reduced to 483 bits after 1-D space mapping. To save several H-matrices in multi-rate communications, a further reduction can be achieved by merging the same shift values with the same memory indices into one before synthesis. That is, except for the 1-D memory space mapping mentioned in Section 5, if the overlapped elements in diverse H-matrices can be preprocessed, a better optimization can be achieved in our synthesis result. In Figure 11, each H-matrix has been mapped into a 1-D memory space. We find that these 1-D memory spaces have the same elements in specific memory indices. The required memory can be more compact after all the overlapped elements are merged into one.

6.2. Design architecture

The architecture of the design example is shown in Figure 12. An H-register, employed for saving a specific H-matrix selected from the four H-matrices, prevents accessing of the non-volatile memory frequently during the communication time. Therefore, the implementation can be divided into two parts, namely non-volatile storage and volatile storage. In Figure 12, the non-volatile part is implemented by sticking the inputs of the 4-input multiplexer to logic high or logic low, instead of using a real ROM block. Before a session of communication commences, the input signal H_select selects a specific 1-D memory space and loads its content into an H-register. During communication, only the H-register needs to be accessed to determine the message addresses, and the non-volatile memory access is thus prevented. In a session of communication, all the shift values can be spanned through the content of the H-register. As shown in Table 4, four diverse H-matrices which provide relatively good error performances are included in the H-library. Since only one H-matrix is required for error correction in a specific session of communication, it is not necessary for all the four H-matrices to be loaded once at a time.

H-matrix	Type	Non-zero elements storage (M × k × Z)	Multiple constructions			1-D memory mapping
			( N , j , k )	Rate	p	( j + k-1 ) z	Reduction factor
H1	MWC-OCS	724 × 8 × 11 = 63712 bits	(1448,4,8)	0.5A	181	11 × 8 = 88 bits	1.38 × 10-3
H2	MWC-OCS	3508 × 8 × 13 = 364832 bits	(7016,4,8)	0.5B	877	11 × 10 = 110 bits	3.01 × 10-4
H3	MWC-OCS	412 × 16 × 11 = 72512 bits	(1648,4,16)	0.75A	103	19 × 7 = 133 bits	1.83 × 10-3
H4	MWC-OCS	1004 × 16 × 12 = 192768 bits	(4016,4,16)	0.75B	251	19 × 8 = 152 bits	7.88 × 10-4
H-library	MWC-OCS	693824 bits				483 bits	6.96 × 10-4
Preprocess	MWC-OCS	693824 bits				348 bits	5.02 × 10-4
Synthesis results	MWC-OCS H-library					152 output pads (memory less and gate free) 13 gates (non-volatile) 16 DFFs (volatile)

Memory-efficient MWC-OCS LDPC codes were proposed to reduce the non-volatile memory demand for H-matrix storage. The described similar codes outperform other recent approaches with huge memory-reduction rates. Compared to CMMB and WIMAX/WLAN, our similar codes have, respectively, achieved 92 and 88% reduction rates in terms of the requirement of memory bits. In the synthesis result of our similar code storage for CMMB, the gain (99.6%) evaluated by gate count is even larger than the gain (92%) estimated by memory bits. In addition, the proposed codes also show relatively good error performances comparable with competitive codes in column-weight 4 constructions. Furthermore, a design example was also synthesized to be every compact for multi-rate H-matrices storage. In implementing wireless applications for multiple communication protocols within a fixed size of memory space, our approach is of good worth. As we have mentioned, even when the huge gain achieved is only a small fraction of the overall decoder, it cannot be considered negligible as the demand for diverse H-matrices storage of multiple communication protocols increases. Especially, for a tiny device with a very limited size of memory space, applying the proposed approach can enhance the capability for supporting many more error correction functions.