Algorithm and hardware design of a 2D sorter-based K-best MIMO decoder

2.1 Notations

We shall use bold lowercase letters for vectors and bold capital letters for matrices. Furthermore, ∥·∥ denotes the L - 2 norm distance or Euclidean distance, (·)^H denotes the Hermitian transpose of a matrix, and (·)^I and (·)^Q respectively denote the in-phase(IP) and quadrature-phase (QP) parts of a signal.

2.2 Channel model and full K-best algorithm

The full K-best finds the transmitted symbol x by solving (2). In this equation, Ω^N denotes W^N possible sets of the transmitted symbol vector x, and z = Q^Hy. Equation 2 is computed through N stages in the order from N to 1, one after another. The n th stage (n = N,…,1) computes the n th partial Euclidean distance (PED_n) in (3) by adding PED_n+1 (i.e., results of the (n+1)th stage) with D_n (i.e., calculated in the n th stage).

Two main tasks - expansion and sorting - will be done in stage n (n = N,…,1) (refer to [5] for details).

The processing of the two first stages (i.e., N and N-1) is illustrated in Figure 1. Notice that K = 1 if n = N.

At the final stage (i.e., stage 1), the sorting is not performed. All K×W values of PED₁ are used for the final decision, whether hard or soft decision. The hard decision method finds the value of {x_N,…,x₁} that is equivalent to the smallest value of PED₁ and decides this value as the decoded data, while the soft decision method calculates the log likelihood ratio (LLR) of all information bits.

3.1 Direct expansion

In the first quarter of the constellation (in which IP and QP parts are both non-negative), we divide the IP space into $\sqrt{\mathfrak{W}}-\mathfrak{1}$ subdomains such as $[\mathfrak{0},{\mathfrak{r}}_{\mathfrak{n}\mathfrak{n}}),[{\mathfrak{r}}_{\mathfrak{n}\mathfrak{n}},\mathfrak{2}{\mathfrak{r}}_{\mathfrak{n}\mathfrak{n}}),\dots ,[\sqrt{\mathfrak{W}}-\mathfrak{2},\infty )$. Each subdomain is associated with a set of $\mathit{\text{ceil}}\left(\sqrt{\mathfrak{L}}\right)$ best values of ${\mathfrak{x}}_{\mathfrak{n}}^{\mathfrak{I}}$. For example, if the modulation is 16-QAM and L = 9, the IP space is divided into [ 0,r_nn), [ r_nn,2r_nn), and [ 2r_nn,∞) subdomains. The corresponding three best values of ${\mathfrak{x}}_{\mathfrak{n}}^{\mathfrak{I}}$ are (1, -1, 3), (1, 3, -1), and (3, 1, -1), respectively (refer to Figure 2a). With QP space and ${\mathfrak{x}}_{\mathfrak{n}}^{\mathfrak{Q}}$, we do similarly.

The L best child nodes per parent node in stage n (n = N,…,1) are directly specified as follows:

Step 1. Calculate f_n that is defined in (4).

Step 2. Determine the IP subdomain that ${\mathfrak{f}}_{\mathfrak{n}}^{\mathfrak{I}}$ belongs to by comparing ${\mathfrak{f}}_{\mathfrak{n}}^{\mathfrak{I}}$ with values such as r_nn, 2r_nn, …, $\left(\sqrt{\mathfrak{W}}-\mathfrak{2}\right){\mathfrak{r}}_{\mathfrak{n}\mathfrak{n}}$. From that, the $\mathfrak{c}\mathfrak{e}\mathfrak{i}\mathfrak{l}\left(\sqrt{\mathfrak{L}}\right)$ best values of ${\mathfrak{x}}_{\mathfrak{n}}^{\mathfrak{I}}$ will be known. If ${\mathfrak{f}}_{\mathfrak{n}}^{\mathfrak{I}}<\mathfrak{0}$, the signs of ${\mathfrak{x}}_{\mathfrak{n}}^{\mathfrak{I}}$ are reversed. Then, we calculate the corresponding DI_n in (5). The ${\mathfrak{x}}_{\mathfrak{n}}^{\mathfrak{Q}}$ and DQ_n are found similarly (refer to Figure 2a).

Step 3. From $\mathfrak{c}\mathfrak{e}\mathfrak{i}\mathfrak{l}\left(\sqrt{\mathfrak{L}}\right)$ best values of ${\mathfrak{x}}_{\mathfrak{n}}^{\mathfrak{I}}$, DI_n, and ${\mathfrak{x}}_{\mathfrak{n}}^{\mathfrak{Q}}$, DQ_n, we compute L best values of x_n and D_n in (5). Let call i_n and q_n as the index numbers of the best values of DI_n and DQ_n, which are already in ascending order. The combination of the sum D_n = DI_n+DQ_n is arranged so that the sum ${\mathfrak{i}}_{\mathfrak{n}}^{\mathfrak{2}}+{\mathfrak{q}}_{\mathfrak{n}}^{\mathfrak{2}}$ increases. Consequently, the results of D_n are approximately in ascending order without sorting (refer to Figure 2b).

To expand L best child nodes from a parent node, the previous works such as [5] firstly finds the center node by rounding the result x_c=f_n/r_nn. It then seeks for L nearest nodes to the center node. The divider is thus required. By comparing as step 2, the proposed algorithm can eliminate the divider f_n/r_nn. Furthermore, by using (5), L values of D_n are obtained from ceil$\left(\sqrt{\mathfrak{L}}\right)$ values of DI_n and DQ_n. The complexity of computing Euclidean distance D_n is reduced.

3.2 Parent node grouping

It is important to know how much should the number of child nodes per parent node (L) be. If L is too large, BER performance is improved. However, the decoder’s complexity is also increased. If L is too small, the BER performance may be too small to fulfill the system requirement.

Notice that once the L best child nodes are directly specified as mentioned in Section 3.1, if L>K, there is no probability that one of the last L-K child nodes of any parent will become the final selection. Thus, selecting L ≤ K is a way to reduce the complexity without trade-off of the performance.

In another aspect, assume that k and c are the index number of the K parent nodes (PED_n+1) and of the L child nodes (D_n) per parent node in stage n, respectively. Because values of PED_n+1 are already sorted in stage n+1, the parent node that has high index k will have a large value of PED_n+1. Thus, its child nodes are expected to have low probability to be selected as one of the K smallest (best) nodes for the next stage. To prove this analysis, we did the simulation and computed the probability (in %) in which a child node might become one of the K best nodes. The result is shown in Figure 3. From this figure, it can be seen that the larger the index k is, the smaller the number of child nodes may be selected.

Based on that fact, we propose a parent node grouping method as follows: The K parent nodes are divided into G groups. Each group has A=K/G parent nodes. Note that K and G should be selected so that K is dividable to G (i.e., mod(K,G) = 0). Group 1 contains the best parent nodes, while group G contains the worst parent nodes. Each parent node of the g th (g 1,2,…,G) group is expanded by L_g child nodes so that L_G < ⋯ < L₁ ≤ K.

3.3 Two-dimensional sorter

Sorting is the major bottleneck of the K-best decoder because of its high complexity. Theoretically, the sorting of n elements requires (n²-n)/2 comparators.

In this subsection, we propose a two-dimensional (2D) sorter which has low complexity, is suitable for hardware resource sharing, and produces approximate result. The 2D sorter for sorting $\mathfrak{C}=\sum _{\mathfrak{g}=\mathfrak{1}}^{\mathfrak{G}}\mathfrak{A}{\mathfrak{L}}_{\mathfrak{g}}$ child nodes is described as follows: we put the C child nodes into an A×B matrix, in which $\mathfrak{B}=\sum _{\mathfrak{g}=\mathfrak{1}}^{\mathfrak{G}}{\mathfrak{L}}_{\mathfrak{g}}$. The j th row of the matrix contains all the child nodes of the j th parent of all groups. The illustration in the case G=3 is shown in Figure 4. The matrix operates through two processes called as row sorting and column sorting, one after the other, as follows:

• ‘Row sorting. The B elements in a row are sorted. The smallest value is located in the left of the row. This sorting is repeated for all rows.

After completing the row and column sorting, the K top-left elements of the sorted matrix are expected to be the best (smallest) values and are selected. A simulation is needed in advance to correctly determine the position of the best candidates.To verify the correctness of the 2D sorter, we did the simulation and measured the probability (in %) in which an element of the sorted matrix might become one of the actual K = 7, K = 14, and K = 21 best nodes. The results are shown in Figure 5. From these results, positions of the 1st to the 7th (yellow color), 8th to the 14th (green color), and 15th to the 21st (blue color) best nodes are one by one determined. The figure also shows that the obtained results (in %) are slightly affected by channel type. However, the influence is too small so that the position of the best nodes is not affected by channel type.

The 2D sorter is suitable for hardware resource sharing because all the rows (columns) do the same task. A circuit which sorts B elements of the 1st row in the 1st cycle can be reused to sort the 2nd, …, A th rows in the 2nd, …, A th cycles.

4.1 Overview architecture

To determine the effectiveness of the proposed algorithm practically, we develop a 4×4 2D sorter-based K- best MIMO decoder for 802.11n and 11.ac systems. The decoder supports five modulation types such as BPSK, QPSK, 16-QAM, 64-QAM, and 256-QAM. After completing exhaustive simulation and considering the trade-off between BER performance and complexity, the decoder is configured as follows:

•  At all stages, we select K = 21, G = 3, A = K/G = 7, L₁ = 4, L₂ = 3, L₃ = 1, B = 8, and C = 56. In the case of 16-QAM, QPSK, and BPSK, which has W<K, the numbers of parent nodes of stages 3, 2, and 1 (denoted by K₃, K₂, and K₁, respectively) are selected as follows: with 16-QAM mode, K₃ = 14 and K₂ = K₁ = 21; with QPSK mode, K₃ = 4, K₂ = 14, and K₁ = 21; and with BPSK mode, K₃ = 2, K₂ = 4, and K₁ = 8.

•  Stage 4 does not use the sorter, while stages 3 and 2 use the proposed 2D sorter with the matrix size of 7 × 8.

•  Soft decision is used to achieve high BER performance.This configuration is illustrated in Figure 6a.

The overview hardware architecture of the decoder is shown in Figure 6b. The ‘STAGE 4’ block computes K best values of PED₄ and the corresponding x₄ in (6). Similarly, the ‘STAGE 3’ block computes K best values of PED₃ and the corresponding {x₄,x₃} in (8). The ‘STAGE 2’ block computes K best values of PED₂ and the corresponding {x₄,x₃,x₂} in (10). The ‘STAGE 1’ block computes C best values of PED₁ and the corresponding {x₄,x₃,x₂,x₁} in (12). The ‘LLR’ block computes the log likelihood ratio. The ‘Multiplier-Less’ block prepares necessary data so that no multiplier will be implemented in all the abovementioned blocks.

4.2 Hardware implementation

To achieve low complexity, in addition to utilize the proposed algorithm, the following implementation points are worth to be noticed.

4.2.1 GAIN-MUX-based multiplier

From (6) to (12), it can be seen that the decoder requires a large number of multipliers to compute r_ijx_j (i = 4,3,2,1;j ≥ i). For example, $\mathfrak{2}\sqrt{\mathfrak{K}}$ multipliers are needed to compute ${\mathfrak{r}}_{\mathfrak{4}\mathfrak{4}}{\mathfrak{x}}_{\mathfrak{4}}^{\mathfrak{I}}$ and ${\mathfrak{r}}_{\mathfrak{4}\mathfrak{4}}{\mathfrak{x}}_{\mathfrak{4}}^{\mathfrak{Q}}$ in stage 4 (see (6)), and the multiplier costs large hardware resource.

To compute r_ijx_j (i = 4,3,2,1;j ≥ i), instead of using the multiplier, we implement GAIN and multiplexer (MUX) as be shown in Figure 7. This figure illustrates the case of multiplying r_ij with m best values of x_j. The left figure shows the conventional method which uses m different multipliers. The right figure is our proposed GAIN-MUX-based multipliers. The input data r_ij firstly goes into the ‘GAIN’ block that amplifies r_ij by the modulation gain D and then by the values of the constellation points such as 1,3,5,…,15. Notice that all the possible values of x_j are {D,3D,…,15D}. The outputs of ‘GAIN’ blocks are then inputted to m MUX blocks. Each MUX is controlled by a select signal of x_j (i.e., denoted by $\mathfrak{s}\mathfrak{e}\mathfrak{l}\text{\_}{\mathfrak{x}}_{\mathfrak{j}}^{\left(\mathfrak{m}\right)}$). If values of ${\mathfrak{x}}_{\mathfrak{j}}^{\left(\mathfrak{m}\right)}$ are {D,3D,…,15D}, values of $\mathfrak{s}\mathfrak{e}\mathfrak{l}\text{\_}{\mathfrak{s}}_{\mathfrak{j}}^{\left(\mathfrak{m}\right)}$ will be {0,1,…,7}. Consequently, the outputs of MUX blocks are equivalent to the outputs of multipliers in the left figure. Meanwhile, hardware cost for MUX is much smaller than that for the multiplier.

The decoder needs multipliers to compute many data, such as ${\mathfrak{r}}_{\mathfrak{4}\mathfrak{4}}{\mathfrak{x}}_{\mathfrak{4}}^{\mathfrak{I}}$, ${\mathfrak{r}}_{\mathfrak{3}\mathfrak{3}}^{\mathfrak{I}}{\mathfrak{x}}_{\mathfrak{3}}^{\mathfrak{I}}$, and ${\mathfrak{r}}_{\mathfrak{2}\mathfrak{2}}{\mathfrak{x}}_{\mathfrak{2}}^{\mathfrak{I}}$, while possible values of ${\mathfrak{x}}_{\mathfrak{4}}^{\mathfrak{I}}$, ${\mathfrak{x}}_{\mathfrak{3}}^{\mathfrak{I}}$, and ${\mathfrak{x}}_{\mathfrak{2}}^{\mathfrak{I}}$ are the same. Thus, one ‘GAIN’ block can be shared among them. The ‘Multiplier-Less’ block implements this ‘GAIN’ block.

4.2.2 Resource sharing

This technique is implemented in STAGE 4, STAGE 3, STAGE 2, and STAGE 1 blocks.

The STAGE 4 block computes K best values of PED₄ and x₄ in (6). Based on the direct expansion method, it finds ceil$\left(\sqrt{\mathfrak{2}\mathfrak{1}}\right)=\mathfrak{5}$ best values of DI₄ and DQ₄ and then adds these values together. Because the processes of finding DI₄ and DQ₄ are similar to each other, they share the same circuit. Figure 8a shows the block diagram inside STAGE 4, in which, ‘BLOCK A’ is shared to find best values of DI₄, ${\mathfrak{x}}_{\mathfrak{4}}^{\mathfrak{I}}$ and DQ₄, ${\mathfrak{x}}_{\mathfrak{4}}^{\mathfrak{Q}}$ in two clock cycles. In other words, the sharing factor of this block is 2. The design of BLOCK A is shown in Figure 8b, in which the ‘SIGN ABS’ block determines the sign and absolute value of $\left|{\mathfrak{z}}_{\mathfrak{4}}^{\mathfrak{I}}\right|$ (and $\left|{\mathfrak{z}}_{\mathfrak{4}}^{\mathfrak{Q}}\right|$). The ‘CONS-LOCAT’ block specifies the subdomain in the constellation that $\left|{\mathfrak{z}}_{\mathfrak{4}}^{\mathfrak{I}}\right|$ (and $\left|{\mathfrak{z}}_{\mathfrak{4}}^{\mathfrak{Q}}\right|$) belongs to. Based on information of the CONS-LOCAT block, the ‘DI/DQ CAL’ block computes the best values of DI₄ and DQ₄, while the ‘XDE-CODE’ block finds the best values of ${\mathfrak{x}}_{\mathfrak{4}}^{\mathfrak{I}}$ and ${\mathfrak{x}}_{\mathfrak{4}}^{\mathfrak{Q}}$.

The STAGE 3 block computes the best values of PED₃ and the corresponding {x₄,x₃} in (8). The block diagram is shown in Figure 8c, in which ‘B1,’ ‘B2,’ and ‘B3’ respectively perform the direct expansion for the 1st → 7th (i.e., group 1), 8th → 14th (i.e., group 2), and 15th → 21st (i.e., group 3) parent nodes. Because all parent nodes in the same group process similarly, they can share the same circuit. Consequently, the B1 block is designed to find L₁ best child nodes of one parent node only. It is then reused in seven clock cycles to complete the direct expansion for seven parent nodes of group 1. The sharing factor is 7. Similarly, the B2 and B3 blocks are shared by seven times. Each B1, B2, and B3 block has the following components: ‘CAL f₃’ computes f₃ in (7), ‘BLOCK A*’ computes DI₃ and DQ₃, and ‘SUM’ computes PED₃ from PED₄, DI₃, and DQ₃ (see (8)).

After each clock cycle, B1, B2, and B3 output the best child nodes of one parent node in all groups. In other words, all elements of one row in the sort matrix (see Section 3.3) are obtained per cycle. Block ‘2D-SORT’ thus requires only a one-row-sorting circuit. This circuit is then shared to sort all seven rows in seven clock cycles. The sharing factor is 7. The hardware design of the 2D-SORT block is shown in Figure 9. The ‘ROW-SORT’ block sorts eight outputs of B1, B2, and B3 per clock cycle. Only four best data are obtained. In the ‘COL-SORT’, the ‘1to7’ collects the best values from ROW-SORT in seven cycles and sorts them. The ‘1to6’ block collects the 2nd best values from ROW-SORT in seven cycles, sorts them, and obtains six best data, so on. The designs of ROW-SORT and ‘1to3’ of COL-SORT are shown in Figure 9b,c, respectively. It can be seen that the 2D-SORT needs only 36 comparators to sort 56 child nodes, which is significantly reduced as compared to (56²-56)/2 = 1,540 comparators if using the full sort.

The architectures of STAGE 2 and STAGE 1 are similar to STAGE 3. The sharing factor of these blocks is 7. However, the 2D-SORT block is not implemented in STAGE 1. Instead, the results of B1, B2, and B3 are directly passed to the LLR block.

5.1 QRD versus SQRD

Figure 10 shows that using SQRD pre-processing helps to improve BER performance by 0.6 dB, 0.8 dB (at BER = 10^-3), and 1 dB (at BER = 10^-2) for cases of K = 21, K = 10, and K = 6, respectively, as compared to the case of using QRD.

5.2 Parent node grouping

Figure 11 shows that the BER performance is insignificantly degraded when ‘L1-L2-L3’ is decreased from 256-256-256 (full K-best) to 9-9-9, 9-6-3, 4-4-4, and 4-3-1. Numerically, the performance degradation of L1-L2-L3 = 4-3-2 is about 0.15 dB as compared to the full K- best (at BER = 10^-3). However, when continuing to reduce the number of child nodes per parent node to L1-L2-L3 = 1-1-1, the performance degradation is about 1.2 dB, which is considerable, as compared to the full K-best.

5.3 2D sorter

Figure 12 shows that the BER performance of S4 NoSort - S32 2D Sort is insignificantly degraded as compared to the case of S4 FullSort - S32 FullSort. The amount of degradation is about 0.08 dB (at BER = 10^-3). In other words, (1) by applying the direct expansion method, the sorter can be eliminated in stage 4, and (2) the 2D sorter is an acceptable approximation of the full sorter. It can be used in trade-off with about 0.08-dB BER performance.

5.4 The proposed decoder

Figure 13 shows the BER of 4×4 MIMO 802.11ac system when applying BLAST MMSE, LRA-MMSE, full K-best (soft decision), and the proposed decoder (soft and hard decisions).

From this figure, it can be seen that for all modulation types (16-QAM, 64-QAM, and 256-QAM), the proposed decoder with soft decision (green line) outperforms the BLAST MMSE (blue line) and LRA MMSE (black line), and is close to the full K-best with soft decision (red line). Numerically, at the observation point of BER = 10^-3, the proposed decoder (with soft decision) is better than BLAST MMSE by 6.7, 3.7, and 2.3 dB, respectively. It is better than LRA MMSE by 1, 0.5, and 0.02 dB, respectively. As compared to the full K-best, the BER performance degradation of the proposed one is about 0.2 dB for all cases. In addition, using soft decision can improve the performance of the proposed decoder by about 2 dB as compared to the hard decision (green line versus pink line).

From this figure, we also see that the BER performance’s gap from the proposed decoder (soft decision) and the full K-best to the LRA MMSE and the BLAST MMSE decreases when the modulation types increase from 16-QAM to 64-QAM and to 256-QAM. That is because the modulation size increases while the K value is fixed to 21. Consequently, the BER performance of the proposed decoder and of the full K-best is expected to be worse as the modulation size increases.

Notice that in cases of BPSK and QPSK, the proposed decoder searches all of the constellation nodes; it thus achieves the same BER as the optimal MLD does.