### Subsampling architecture

The traditional subsampling receiver mainly consists of a low noise amplifier (LNA), a sample and hold mixer, a complex bandpass filter, a clock generation, and an ADC. Usually, a single-ended input signal can be transferred to differential signal by an off-chip balun, which increases the size of system. And the sample and hold mixer adopts simple MOS switches and sampling capacitors to achieve frequency conversion, generating serious nonlinear effects and charge injection. Moreover, it adopts a high local sampling frequency to down-convert RF signal to IF signal. Therefore, the clock generation is needed to provide the high clock sampling frequency, which increases the power consumption of the subsampling receiver. In addition, a clock generation based on high BAW resonators increases the size of the system.

For the requirements of wireless communication applications of IoT, such as low data rate, low power consumption and high integration, a subsampling receiver adopts a simple ASK modulation. In addition, a 1 bit ADC (such as comparator) can be used to demodulate baseband signal. Compared to traditional subsampling receiver, the proposed subsampling receiver architecture is shown in Fig. 6, which includes a balun low noise amplifier (balun-LNA), a two-stage passive sample and hold (*S*/*H*) mixer, an intermediate frequency amplifier (IFA), two down-conversion filters combined with a finite input response filter and an infinite impulse response filter, 1 bit ADCs and a clock generator. The balun-LNA not only achieves a high gain and a low noise figure, but also provides the differential output signal, without using the off-chip balun. And the two-stage passive *S*/*H* mixer adopting complementary switches and capacitors can sample and translate RF signal to IF signal, which reduces nonlinear effect and charge injection. In order to reduce folding noises, IF should be further filtered and decimated to baseband by down-conversion filters, and baseband is demodulated and processed in digital circuits. A clock generator can provide local sampling signal, which can be translated to the clock sampling signal by two frequency dividers and the decimated sampling signal by D flip-flop. With the control of clock signal, RF signal is translated to IF by the *S*/*H* mixer and further decimated to baseband by the down-conversion filters.

According to the above subsampling theory analysis, the local oscillation frequency is 80 MHz with a sampling frequency of 40 MHz, and the decimated sampling rate is 10 MHz. When RF input signal adopts ASK modulation at a data rate of 1 Mbps and ratio of minimum signal to noise SNR_{min} is about 13 dB, the total noise figure NF of the subsampling receiver could be express as follows:

$$ \mathrm{N}\mathrm{F}=-\left(-174\mathrm{d}\mathrm{B}\mathrm{m}+10 \log \mathrm{B}\mathrm{W}+{\mathrm{SNR}}_{\min}\right)+{P}_{\mathrm{sens}} $$

(12)

where BW is the bandwidth of filter, *P*
_{sens} is the sensitivity of the subsampling receiver. From the expression (12), the total noise figure NF is determined by BW, SNR_{min}, and *P*
_{sens}. When the sensitivity of the subsampling receiver is −85 dBm with the 2-MHz bandwidth of filter, NF is 13 dB. Therefore, NF should be less than 9 dB, considering 3~4 dB loss. In order to meet the requirements of high sensitivity, low noise figure, and low power of the system, the total power consumption of the subsampling receiver should be less than 4 mW and the total voltage gain of the system cannot be less than 60 dB when the subsampling receiver achieves −85 dBm sensitivity at 10^{−3} BER. Further, with high noise figure of *S*/*H* mixer, the voltage gain of LNA should be more than 27 dB which reduces the total noise figure of the subsampling receiver.

### Balun-LNA

In order to reduce the folding noise of the subsampling receiver, RF input signal should be filtered by the bandpass filter before *S*/*H* mixer. Although off-chip SAW/BAW filter can achieve high *Q* to filter the interference and reduce the anti-aliasing noises, it is difficult to improve integration of the system. By using the frequency selective network and choosing the proper sampling frequency, the folded noises can be reduced.

With restraining a common-mode noise and reducing parasitic couplings, differential configuration is widely used in the LNA circuits. However, off-chip baluns used to achieve differential signal, which degrades integration of the system. Traditionally, an active balun-LNA adopts the common-gate and common-source cascade topology to provide the differential signal output. However, it is difficult to achieve a high voltage gain and generate the differential signal of phase opposite and equal amplitude under process variation. Therefore, the proposed balun-LNA adopting the noise-cancelling technique is shown in Fig. 7, which can acquire a differential signal output. Firstly, transistor M1 achieves high gain and better input impedance matching, with the inductors *L*
_{s}, *L*
_{g}, and capacitor *C*
_{g}. And then transistors M2 and M3 are consisted of the common-gate common-source differential output topology, achieving noise cancelling and distortion cancelling. A single-end RF signal is transferred from the drain of M1 to the source of M2 and the gate of M3 through the capacitor *C*
_{c}, achieving differential output signal. Capacitor *C*
_{b} provides AC coupling to ground and bias supply voltage makes enough current, which avoids using the larger inductor *L* to balance the current of differential output topology. As the first block in the subsampling receiving chain, the performance of the balun-LNA is of great importance, which can determine the noise figure and the power consumption of the whole system. Considering requirements of wireless communication for IoT application, the voltage gain of the balun-LNA should be more than 25 dB, and the noise figure and the power consumption of the balun-LNA should be less than 2 dB and 2.5 mW, respectively. Moreover, the amplitude and the phase mismatch of the differential signal output remains, respectively, within 0.5 dB and 5°.

In order to analyze the noise figure of the balun-LNA in detail, the noise figure of every stage of LNA is listed, respectively [16]. Firstly, the noise figure NF1of M1 can be calculated as follows:

$$ \mathrm{N}\mathrm{F}1=1+\frac{2}{\sqrt{5}}\cdotp \frac{w\left({C}_{gs1}+{C}_g\right)}{g_{m1}}\cdotp \sqrt{\gamma \delta \left(1-{\left|c\right|}^2\right)} $$

(13)

where the *γ*, *δ*, *c* are process parameters. NF1 is determined by the transconductance *g*
_{m1} of M1 and the gate-source capacitance *C*
_{gs1} and capacitor *C*
_{g}.

Secondly, the typical CG–CS topology is widely used in LNA, which has been analyzed in detail [15]. The noise figure NF2 of the CG–CS topology can be calculated as follows:

$$ \begin{array}{l}\mathrm{N}\mathrm{F}2=1+\frac{\gamma {g}_{\mathrm{m},\mathrm{C}\mathrm{G}}\cdotp {\left({R}_{\mathrm{CG}}-{R}_{\mathrm{S}}\cdotp {g}_{\mathrm{m},\mathrm{C}\mathrm{S}}\cdotp {R}_{\mathrm{CS}}\right)}^2}{R_S\cdotp {A^2}_{V,2}}+\frac{\gamma {g}_{\mathrm{m},\mathrm{C}\mathrm{S}}\cdotp {R^2}_{\mathrm{CS}}\cdotp {\left(1+{g}_{\mathrm{m},\mathrm{C}\mathrm{G}}\cdotp {R}_{\mathrm{S}}\right)}^2}{R_{\mathrm{S}}\cdotp {A^2}_{V,2}}\\ {}\kern5.25em +\frac{\left({R}_{\mathrm{CG}}+{R}_{\mathrm{CS}}\right)\cdotp {\left(1+{g}_{\mathrm{m},\mathrm{C}\mathrm{G}}\cdotp {R}_{\mathrm{S}}\right)}^2}{R_{\mathrm{S}}\cdotp {A^2}_{V,2}}\end{array} $$

(14)

Assuming that the transconductance *g*
_{m,CS} is *n* times bigger than the transconductance *g*
_{m,CG} and the load resistor *R*
_{CG} is *n* times bigger than the load resistor *R*
_{CS}, which can achieve the equal voltage gain. When transistor M3 is matched, *R*
_{S} is the reciprocal of the transconductance *g*
_{m,CG} (*R*
_{S} = 1/*g*
_{m,CG}). Therefore, the noise figure NF2 and the voltage gain *A*
_{
V,2} of the CG–CS topology can be, respectively, rewritten as follows:

$$ \mathrm{N}\mathrm{F}2=1+\frac{4\gamma {g}_{\mathrm{m},\mathrm{C}\mathrm{G}}\cdotp \frac{{R^2}_{\mathrm{CG}}}{n}}{R_{\mathrm{S}}\cdotp {A^2}_{\mathrm{V}}}+\frac{4\left(1+\frac{1}{n}\right){R}_{\mathrm{CG}}}{R_{\mathrm{S}}\cdotp {A^2}_{\mathrm{V}}} $$

(15)

$$ {A}_{\mathrm{V},2}=2{g}_{\mathrm{m},\mathrm{C}\mathrm{G}}\cdotp {R}_{\mathrm{CG}} $$

(16)

where NF2 is determined by the transconductance *g*
_{m,CG} of M3 and the load resistor *R*
_{CG}. According to the impeding matching condition, the transconductance *g*
_{m,CG} is 20 mS and the *R*
_{S} is 50*Ω. γ* is about 4/3, and the load resistor *R*
_{CG} is about 1000*Ω* so as to acquire high voltage gain. Based on the simulation of Eqs. (15) and (16) by using the Matlab, NF2 of the CG–CS topology is clearly shown in Fig. 8. The noise figure NF2 becomes smaller by increasing the transconductance ratio *n* (*n* = *g*
_{m,CS}/*g*
_{m,CG}). For example, when the transconductance ratio *n* is more than 4, NF2 of the system can be less than 1.5 dB. However, it is difficult to achieve transistors mismatching for higher *n*.

Considering impeding matching condition of CG transistor M3, the noise figure cannot be further reduced. However, based on the inductively degenerated stage, the proposed balun-LNA achieves the lower noise figure for the large *R*
_{S} and small *g*
_{m,CG}. According to the cascaded formula of noise figure, the total noise figure of the balun-LNA can be expressed as follows:

$$ \mathrm{N}\mathrm{F}=\mathrm{N}\mathrm{F}1+\frac{\mathrm{NF}2-1}{A_{V,1}} $$

(17)

Usually, the inductively degenerated cascade configured LNA has high voltage gain *A*
_{
V,1}. Therefore, noise figure NF1 has an important effect on the total noise figure NF of LNA.

###
*S*/*H* mixer

Generally, differential sample and hold (*S*/*H*) mixer circuits include MOS switches and sampling capacitors. Without the high *Q* filter before *S*/*H* mixer, there are many folding noises affecting the information signal. In order to restrain the effect of folding noises, the proposed two-stage passive *S*/*H* mixer is shown in Fig. 9. Complementary switches constituted by NMOS and PMOS can reduce the charge injection. The differential output signal of the balun-LNA is sampled and converted to quadrature I path and *Q* path IF signals by the passive *S*/*H* mixer, respectively, without using high power-consuming RF PLL. However, after the first *S*/*H* mixer, RF interference signal still exists in the sampled signal. The second *S*/*H* mixer with the opposite clock sampling signal can be used to further fulfill the frequency conversion, which would relax the complexity of the following stages. Although the sampling capacitors should be large enough to reduce the *kT*/*C* noise, it would increase the size of the *S*/*H* mixer. Therefore, the sampling capacitor should be tradeoff between noise and size of the system. For the application of IoT, the clock sampling frequency of 40 MHz can be used with the sampling ratio of 20, based on the analysis of the sampling frequency. And the total noise figure of *S*/*H* mixer and second-order filter can be obtained as follows:

$$ {\mathrm{NF}}_{\mathrm{mixer}}=\frac{S_{\mathrm{in}}}{N_{\mathrm{in}}}\cdotp \frac{N_{\mathrm{out}}}{S_{\mathrm{out}}}\approx 1+3.3\cdotp \frac{N^2}{Q^2}+\frac{1}{2{R}_{\mathrm{s}}\cdotp {C}_{\mathrm{s}}\cdotp {f}_{\mathrm{s}}} $$

(18)

where *Q* is the quality factor and *R*
_{s} is the resistor of an ideal voltage source, and NF is determined by *C*
_{
s
} and *f*
_{
s
}. Based on the simulation of Eq. (18) by using the Matlab, the total noise figure NF_{mixer} of *S*/*H* mixer is clearly shown in Fig. 10. When *Q* is constant, noise figure becomes smaller by increasing sampling local frequency *f*
_{s} or sampling capacitor *C*
_{s}. However, the high sampling frequency *f*
_{s} or large sampling capacitor *C*
_{s} increases the complexity of the system. Therefore, it is of great importance to choose the proper local sampling frequency for the subsampling receiver. For example, the sampling capacitor *C*
_{s} of 1 pF can be adopted for the system.

### IFA and down-conversion filters

After frequency down-conversion of the *S*/*H* mixer, the weak IF signal should be amplified by the intermediate frequency amplifier (IFA). Traditionally, an operational amplifier (OPA) with resistance capacitance (RC) feedback used to amplify the IF signal, at the cost of increasing the size and the power consumption of the subsampling receiver. With two-stage passive *S/H* mixer reducing folded noises, the schematic of the proposed single-stage IFA is shown in Fig. 11a, which is a simple two-stage amplifier. The input signal is amplified by the NMOS common-source amplifier with the current mirror load and the PMOS common-source amplifier with the resistive feedback [39]. IFA not only achieves the high voltage gain and reduces the power consumption but also acquires high isolation between the *S/H* mixer and the following stages. In addition, the resistive feedback configuration can improve the stability and provide enough phase margin which sacrifices a little noise figure of IFA.

In order to further reduce the folding noises emerging in the system, the typical complex down-conversion filters filter the frequency down-conversion signal. However, the lower the sampling frequency is, the smaller the orders of the down-conversion filters are. With the clock sampling frequency of 40 MHz for the subsampling receiver, the proposed discrete time filtering combined with finite input response (FIR) filter and infinite impulse response (IIR) filter is shown in Fig. 11b. For example, four-tap FIR filter mainly includes MOS switches and the sampling capacitors, which can achieve a high *Q* at the IF. Firstly, IF signal can be sampled and hold in capacitors *C*
_{1} ~ *C*
_{4} for a period. And then the sampled signal can be charged into the total capacitor *C*
_{5} and integrated into capacitor *C*
_{6} to output differentially, and the sizes of MOS transistors and sampling capacitors are the same so as to avoid the mismatch. Furthermore, FIR filter can transfer IF signal to baseband by using the decimated clock sampling signal. With the four-tap samplers, FIR filter can also achieve the function of bandpass filter, which has nulls at all multiples of sampling frequency and maximum at all odd multiples of intermediate frequency. And the decimating sampling rate becomes a quarter sampling frequency, which can relax the requirements of ADC. In addition, the transfer function *H(z)* of FIR filter is expressed as follows:

$$ H(z)=1-{z}^{-1}+{z}^{-2}-{z}^{-3}\kern1.5em z={e}^{jw{T}_s} $$

(19)

where *T*
_{
s
} is the sampling cycle of four-tap FIR filter. The charge stored in the sampling capacitors can generate infinite impulse response (IIR), which has maximum at all multiples of sampling frequency and minimum at all odd multiples of intermediate frequency. Although the IIR filter reduces *Q*, it can still achieve maximum at all odd multiples of intermediate frequency.

### Clock generator and 1 bit ADC

A clock generator usually adopts RF PLL to achieve the local sampling signal, which increases the complexity and the power consumption of the system. Therefore, the proposed clock generator has high integration and low power consumption shown in Fig. 12, which mainly includes the amplifier stages, buffers, and D flip-flop. Firstly, differential input signal can be shaped and amplified by the amplifier stages for LO signal. And then D flip-flops using the setting pulse excitation can generate the phased clock signal into *clk*
_{1}, *clk*
_{1b
}, …, *clk*
_{4b
} with the buffers. The waveforms of clock sampling generator can be shown in Fig. 13, and *clk*
_{1} ~ *clk*
_{4} and *clk*
_{1b
} ~ *clk*
_{4b
} can respectively decimate IF signal to quadrature *I*/*Q* output. To reduce the clock jitter, one clock is used to generate the clock sampling signal.

Finally, an ADC, the last block in the receiver, is used to demodulate signal. For the subsampling receiver of IoT application, 1 bit ADC such as comparator can be adopted to demodulate the simple ASK modulation signal. In addition, parallel NMOS and PMOS differential pairs of comparator are adopted to demodulate the baseband.