RF low power subsampling architecture for wireless communication applications
© Meng et al. 2016
Received: 2 February 2016
Accepted: 24 April 2016
Published: 4 May 2016
With the increasing demands of wireless communication, flexible, complex, and diversified wireless communication applications are required. However, the difficulty of enabling new wireless communication applications is the lack of low power radio frequency (RF) transmission devices, especially the RF receiver. In order to alleviate this problem, an RF low power subsampling architecture for wireless communication applications is proposed in this paper. This subsampling architecture adopts a single-ended to differential configured balun low noise amplifier (balun-LNA), a subsampling mixer with high sampling ratio and a finite input response (FIR) filter and infinite impulse response (IIR) filter achieving frequency down-conversion, avoiding using high power-hungry blocks. Based on a subsampling theory, an optimum sampling frequency for the subsampling architecture is necessary to relax the complexity of the system. For the application of internet of things (IoT) wireless communication, the paper provides the implementation of the subsampling receiver solutions to get a tradeoff between power consumption, gain, noise, and sensitivity. It can achieve −85 dBm sensitivity for an amplitude shift keying (ASK) modulation at the data rate of 1 Mbps with the clock sampling frequency of 40 MHz. Finally, the theoretical analysis and simulation results show that the performance of the subsampling architecture has several advantages over others.
Thanks to the evolvement of the CMOS technology, the RF integrated circuits can improve integration and reduce chip area greatly. With the improving demands for wireless communication and the emerging new technologies in recent few years, there is growing attention on sub 1 GHz Industrial, Scientific, and Medical (ISM) bands . Different regulations are applied in different countries, for example, in the USA, the band from 902 to 928 MHz is adopted, with central frequency 915 MHz, while in Europe and China, the bands from 863 to 868 MHz and 755 to 787 MHz are applied, respectively [1, 2]. Most of these standards focus on high integration, low power, low cost, and multi-mode . Especially, low power and high flexibility are of great importance [4, 5].
Although some low power architectures of receiver have been reported, such as direct conversion architecture and low intermediate frequency (IF) architecture [6–8], highly power-hungry blocks such as LO and RF PLL are still existing in the circuits. Fortunately, the concept of new sampling technique is introduced in , called software-defined radio (SDR), which can directly digitize and demodulate all signal from the antenna by A/D converter (ADC). Although this sampling technique can massively reduce power consumption of the system without using RF/analog blocks, it increases the memory of ADC which cannot be achieved by using the existing technologies. Moreover, a specific architecture of new RF sampling approaches can directly down-convert RF signals to baseband signals and achieve signal processing and demodulation in the digital circuits, which can minimize the number of RF and analog blocks [10–12]. For example, RF front-end mainly includes a low noise amplifier and a mixer, which achieves subsampling frequency conversion with clock down-sampling with embedded filtering . However, the fixed filters restrict flexibility of the receiver, which cannot be suited for more channel transmission.
Meanwhile, regardless of RF PLL, subsampling receivers have great advantages in terms of power consumption and flexibility by adopting low sampling frequency [13, 14]. For example, the multi-channel receiver with channel filtering at RF has been reported in , which can achieve −78 dBm sensitivity at 10−3 BER for BFSK modulation. However, the architecture based on the BAW resonator has been implemented, which cannot be integrated for the system. In order to improve integration of the subsampling receiver, the number of extra exponents should be minimized. An active balun-LNA with the noise-cancelling technique instead of off-chip balun can be used [15–17]. For example, the active balun-LNA for GPS can exhibit a power consumption of 3.6 mW and a noise figure of 1.8 dB . Moreover, low supply voltage can make power consumption further reduced [18, 19], with the 0.5 V supply voltage, the total power consumption of the receiver is about 1.15 mW . However, low supply voltage can lead to the nonlinear effects and increase the noise figure of the system . In addition, a quadrature down-conversion technique can greatly improve efficiency of signal frequency conversion, such as subsampling receiver with Q-enhanced RF filtering exhibiting −87 dBm sensitivity at 10−3 BER .
In this paper, design of the subsampling architecture should be tradeoff between integration, sensitivity, noise figure, and power consumption for the application of IoT. In order to solve the problem of noise folding, the subsampling receiver with integrated filter before the subsampling mixer can be used. In terms of sensitivity and integration of the system, the balun-LNA based on the inductively degenerated structure is used to achieve high voltage gain and low noise figure. And it adopts the common-gate and common-source cascade topology to provide differential output signal. Moreover, the sampling frequency with high sampling ratio can be used to further reduce the power consumption. And quadrature sampling technique can acquire high energy efficiency. Therefore, the subsampling architecture with on-chip balun-LNA is proposed in this paper, which can achieve the quadrature sampling frequency conversion by low sampling frequency. This paper is organized as follows: a brief overview of related works is described in Section 2. And the theory analysis of it is introduced in Section 3. The proposed RF subsampling receiver and its building blocks are introduced in Section 4. The performance of the subsampling receiver is exhibited in Section 5. Finally, conclusions and discussion are drawn in Section 6.
2 Related works
Traditionally, an RF subsampling architecture can use a subsampling mixer to achieve frequency conversion, like a superheterodyne receiver. And it still adopts the synthesizer to provide sampling signal . Moreover, a sampling clock jitter or high noise figure cannot be avoided, because of many folded noises emerging in the system. In addition, high sampling frequency with low sampling ratio used to down-convert RF signal to intermediate frequency or baseband, which can increase the complexity and power consumption of the system .
Nowadays, some new techniques, such as high Q filter and high sampling ratio, can be used to achieve high sensitivity, high integration, low noise, and low power consumption for the subsampling architecture . For example, the subsampling receiver with bandpass anti-aliasing filtering can achieve lower power consumption and more flexible than direct conversion or low-IF receivers . Usually, RF subsampling architectures include voltage sampling and charge sampling techniques . Firstly, the charge sampling techniques adopt the charge charging and discharging to achieve frequency conversion, which has more advantages at phase linearity and clock jitter in high frequency and wideband fields . For example, a reconfigurable IF to DC subsampling receiver architecture described in  targets 60 GHz band. And a cascaded charge-domain sampling mixer can achieve an 80-dB suppression of aliasing interferences while consuming 1.08 mA . However, it is difficult to acquire high sensitivity and low noise figure with the charge sampling techniques, because of low voltage gain and many folded noises. And there are many charging capacitors used in the circuits, which can increase the complexity and size of the system. Recently, Xu et al. [29–31] proposed a crowdsensing-based wireless communication data processing methods and be proved with good performance.
While the voltage sampling architecture adopts the voltage value sampling and holding to achieve frequency conversion, which can be widely used in the narrowband systems . For example, subsampling architecture for GPS receiver has been reported in , which has a low noise figure of 3.8 dB and noise figure loss after the subsampling mixer is less than 1 dB. However, the complexity and power consumption of the system can be increased by RF filter, which has a high gain of 25 dB. In order to further reduce power consumption of the receiver, high sampling ratio can be used in the subsampling receiver. As an example, subsampling mixer with integrated filtering, for an RF input frequency of 2.42 GHz with a sampling frequency of 100 MHz, achieves a high sampling ratio of 20 . However, the parallel resonant LC filter with low Q cannot effectively restrain noise aliasing, which results in high noise figure. Moreover, RF signal can be translated to intermediate frequency or baseband by low sampling frequency, which generates many folding noises in subsampling architectures . Thus, bandpass filter before a subsampling mixer should be used to reduce the noise folding. As an example, a 2.4-GHz RF sampling receiver was reported with an input sampling rate of 1072 MS/s , which can fulfill the signal demodulation. However, the size and the power consumption of the system would be increased by high sampling frequency and complex down-conversion filter. And a high precision ADC is used to improve dynamic range of the system. Such as a continuous-time (CT) delta-sigma modulator (DSM) can demodulate signal for RF subsampling receivers, which can achieve high dynamic range of the modulator for OSR = 64 at the cost of high complexity of the system . In order to achieve multi-channels and multi-standard applications, a flexible subsampling frequency can be adopted to down-convert RF signal to intermediate frequency or baseband. For example, multi-standard RF subsampling receiver architecture is reported in , which includes two subsampling stages: first stage with the fixed subsampling frequency and second stage by a tunable IF sampling frequencies clock. It can achieve frequency conversion for a GSM, UMTS, and IEEE-802.11g multi-standard receiver. However, a tunable bandpass RF filter and an IF bandpass filter increase the complexity of the system. In order to further improve the sensitivity and reduce the power consumption of the receiver, high sampling ratio and high Q filter can be used in the subsampling receiver. For example, a subsampling receiver can achieve −91 dBm sensitivity at 10–3 BER for pi/4-DQPSK modulation with low power . However, Q enhancement with the tuning LNA can increase the complexity of the system. Taking the above problems into consideration, the detail analysis for the RF subsampling architectures should be introduced.
3 RF subsampling architecture and theory
3.1 Subsampling theory
3.2 Voltage sampling and charge sampling
From (7), the translated frequency has a maximum at DC and nulls at the n times of f s (n is integer), which can avoid the noise aliasing.
From (8), Sin () function only depends on the f s, and the integration window of the charge sampling architecture can be depended on sampling ratio f/f s. It has a maximum at DC and minimum at every multiple f s.
Based on the above different frequency response of voltage sampling and charge sampling techniques, the −3 dB bandwidth of voltage sampling circuit is determined by the time constant τ, while charge sampling architecture just depends on integral window width.
3.3 Noise analysis
There are two main noises: thermal noise and flick noise in the subsampling architecture. With more harmonic mixing of subsampling frequency f s, noise folding would seriously affect noise figure of the system. In addition, the flick noise can be ignored in low-IF system.
According to the above analysis, the charge sampling architecture has more advantages in the high frequency and wideband receiver architecture. While the voltage sampling capacitor and resistor can be smaller enough to achieve better integration and higher gain. In order to simplify the structure and improve the flexibility of the system, the voltage sampling architecture is good suitable for narrowband and low frequency fields, especially IoT application.
4 Subsampling architecture and circuits design
4.1 Subsampling architecture
The traditional subsampling receiver mainly consists of a low noise amplifier (LNA), a sample and hold mixer, a complex bandpass filter, a clock generation, and an ADC. Usually, a single-ended input signal can be transferred to differential signal by an off-chip balun, which increases the size of system. And the sample and hold mixer adopts simple MOS switches and sampling capacitors to achieve frequency conversion, generating serious nonlinear effects and charge injection. Moreover, it adopts a high local sampling frequency to down-convert RF signal to IF signal. Therefore, the clock generation is needed to provide the high clock sampling frequency, which increases the power consumption of the subsampling receiver. In addition, a clock generation based on high BAW resonators increases the size of the system.
In order to reduce the folding noise of the subsampling receiver, RF input signal should be filtered by the bandpass filter before S/H mixer. Although off-chip SAW/BAW filter can achieve high Q to filter the interference and reduce the anti-aliasing noises, it is difficult to improve integration of the system. By using the frequency selective network and choosing the proper sampling frequency, the folded noises can be reduced.
Usually, the inductively degenerated cascade configured LNA has high voltage gain A V,1. Therefore, noise figure NF1 has an important effect on the total noise figure NF of LNA.
4.3 S/H mixer
4.4 IFA and down-conversion filters
4.5 Clock generator and 1 bit ADC
Finally, an ADC, the last block in the receiver, is used to demodulate signal. For the subsampling receiver of IoT application, 1 bit ADC such as comparator can be adopted to demodulate the simple ASK modulation signal. In addition, parallel NMOS and PMOS differential pairs of comparator are adopted to demodulate the baseband.
5 System performance
The proposed subsampling architecture for the RF receiver is implemented, based on the transistor models of the United Microelectronics Corporation (UMC) 65 nm CMOS technology process by using the Cadence. In order to reduce the power consumption of the system, low threshold voltage NMOS and PMOS transistors were used to simulate the performance of the system-level. Because of many sampling capacitors in the subsampling blocks, especially discrete time filtering combined with FIR filters and IIR filters, the smallest size of sampling capacitor was used to reduce the size of the system. Therefore, the core die area of the subsampling receiver is 1.1 mm*0.9 mm, including I/O pads with ESD protected. For the application of IoT wireless communication, the proposed subsampling receiver operates at the RF signal frequency of 780 MHz with the bandwidth of 20 MHz and ASK signal at a data rate of 1 Mbps is used as the RF input modulation signal. The frequency down-conversion of the system can be achieved easily and flexibly by choosing the sampling frequency, based on input RF signal.
5.1 Current consumption
Current consumption of receiver
1 bit ADC
5.3 System performance
MWSCAS 13 
JSSC 13 
JSSC 13 
ISSCC 14 
JSSC 12 
The proposed subsampling architecture for the RF receiver achieves frequency down-conversion and signal demodulation for wireless communication applications. From the aspects of system architecture, sampling principle and noise figure, the proper clock sampling frequency of 40 MHz is used to transfer the RF signal to the quadrature I path and Q path IF signals, respectively, at low power operation. Moreover, the balun-LNA and the passive S/H mixer without using RF PLL can guarantee high voltage gain and low noise figure of the subsampling architecture. Considering other performances, such as power consumption, voltage gain, noise figure, and sensitivity, the proposed architecture is well suited for the narrowband wireless communication applications. Further, low voltage supply and the advanced CMOS technologies reduce power consumption of the system significantly.
The noise figure of the system is further improved by using the Q enhancement technique. Although the receiver has already exhibited good performance with the simple ASK modulation and the sampling ratio of 20, more advanced modulation and the higher sampling ratio can be used to further improve the performance of the system.
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