A general neuro-space mapping technique for microwave device modeling

Microwave transistors are key components in the next generation wireless communication systems [1–4], such as cognitive multiple-input multiple-output (MIMO) systems [5–7], and cognitive relay network [8, 9]. With the increasing complexity of communication circuit and system structure, designers rely more heavily on computer-aided design (CAD) software to achieve efficient design. Microwave device models are essential to CAD software. The accuracy of these models can even decide whether the communication circuit and system design is successful or not. Due to rapid technology development in semiconductor industry, new microwave devices constantly arrive. Models suitable for previous devices may not fit new devices well. There is an ongoing need for new accurate models.

In recent years, neuro-space mapping (Neuro-SM) technique [10] combining artificial neural networks [11] with space mapping [12] has been recognized in microwave device modeling with the advantages of good efficiency and accuracy. In Neuro-SM, neural networks are used to automatically map and modify an existing equivalent circuit model also called coarse model to a desired/accurate model through a process named training. In order to fulfill the needs of the increased modeling complexity and the industry’s increasing need for tighter accuracy, several improvements on the basis of [10] were subsequently studied to enhance the modeling accuracy and efficiency, such as Neuro-SM with the output mapping [13], dynamic Neuro-SM [14], and analytical Neuro-SM with sensitivity analysis [15]. Neuro-SM with the output mapping [13] was introduced, through incorporation of a new output/current mapping, for modeling of microwave devices. Compared to the Neuro-SM presented in [10], Neuro-SM with the output mapping is more suitable for modeling nonlinear devices with more nonlinearity due to the additional and useful degrees of freedom from the output mapping neural network. In order to accurately model nonlinear devices which have higher order dynamic effects (e.g., capacitive effect or non-quasi-static effect) than that of the coarse model, dynamic Neuro-SM was introduced [14]. However, when the modeling devices have both more nonlinearity and high order dynamics, in such case, even though existing Neuro-SM [13, 14] is used to map the coarse model towards the device data, the match between the trained Neuro-SM models and the device data may be still not good enough. More effective Neuro-SM methods need to be investigated to overcome the accuracy limit of the Neuro-SM presented in [13, 14].

In this paper, we propose a more generalized Neuro-SM approach including not only static mapping but also dynamic mapping, and considering both voltage mapping and current mapping for the first time. This paper is a further expansion of the work in [13, 14]. Compared to [13] where only static mapping is used, the proposed technique is more suitable for modeling nonlinear devices with higher order dynamic effects and non-quasi-static effect that may be missing in the coarse model due to inclusion of dynamic mapping. Compared to [14], the general Neuro-SM considers not only input voltage mapping, but also output current mapping, further refining the existing coarse model. In this way, well trained general Neuro-SM model can represent the dynamic behavior and large-signal nonlinearity of the microwave devices more accurately than the coarse model, Neuro-SM model with the output mapping [13], as well as dynamic Neuro-SM model [14]. The modeling results of a real 2 × 50 μm GaAs pseudomorphic high-electron mobility transistor (pHEMT) demonstrate the correctness and validity of the proposed general Neuro-SM technique.

Suppose the existing equivalent circuit model is a rough approximation of the behavior of the microwave device. We name this existing model as the coarse model. Let the desired model that accurately matches the device data be called the fine model. Just take field effect transistor (FET) modeling as an example, let the gate and drain voltages and currents of the coarse model be defined as v _c  = [v_c1, v_c2] ^T and i _c  = [i_c1, i_c2] ^T , respectively. Let the terminal voltages and currents of the fine model as v _f  = [v_f1, v_f2] ^T and i _f  = [i_f1, i_f2] ^T , respectively.

Suppose the total number of voltage delay buffers at gate and drain be the same and both equal to N _v . Let τ be the time delay parameter. To represent time-domain behavior, the time parameter t is introduced. Figure 1 illustrates the signal flow of the general Neuro-SM model. At first, the present voltages of the fine model v _f (t) as well as their historyv _f (t − τ), v _f (t − 2τ), …, and v _f (t − N _v τ) are mapped into the coarse model voltages v _c (t). Because the formula of the mapping is unknown and usually nonlinear, a neural network is used to learn and represent the mapping. While the Neuro-SM presented in [10] uses a static neural network such as multilayer perceptron (MLP), we propose to use a time delay neural network (TDNN) to map the coarse model to fine model. In functional form, v _c (t) can be described as

$$ {\boldsymbol{v}}_c(t)={\boldsymbol{f}}_{\mathrm{ANN}}\left({\boldsymbol{v}}_f(t),{\boldsymbol{v}}_f\left(t-\tau \right),\dots, {\boldsymbol{v}}_f\left(t-{N}_v\tau \right),{\boldsymbol{w}}_1\right),{N}_v\ge 0\kern0.2em $$

(1)

where f_ANN represents the input/voltage mapping neural network, and w ₁ is a vector containing all the weights of the input mapping neural network. As seen from Eq. (1), voltages at gate and drain of the coarse model depend on not only the present voltages of the fine model, but also their history signals making the proposed technique more suitable for modeling the dynamic behavior of the nonlinear devices. Then, after the coarse model computation, the coarse model currents i _c (t) can be obtained. Suppose the total number of current delay buffers at gate and drain be the same and both equal to N_c. At last, i _c (t) and their history i _c (t − τ), …, i _c (t − N _c τ) as well as the present voltages of the fine model v _f (t) are mapped by another TDNN to the external currents as

$$ {\boldsymbol{i}}_f(t)={\boldsymbol{h}}_{\mathrm{ANN}}\left({\boldsymbol{v}}_f(t),{\boldsymbol{i}}_c(t),{\boldsymbol{i}}_c\left(t-\tau \right),\dots, {\boldsymbol{i}}_c\left(t-{N}_c\tau \right),{\boldsymbol{w}}_2\right),{N}_c\ge 0\kern0.1em $$

(2)

where h_ANN represents the output/current neural network, and vector w₂ contains all the output mapping neural network weights. Compared to [14], the new output neural network mapping further refines the coarse model current signals to produce the fine model outputs. The combined dynamic voltage mapping neural network, coarse model, and dynamic current mapping neural network is called the general Neuro-SM model.

The proposed general Neuro-SM is more general than Neuro-SM technique presented in [10, 13, 14]. While N _v  = 0, then the general Neuro-SM model without the output mapping is static Neuro-SM model [10]. While N _v  = 0 and N _c  = 0, then the general Neuro-SM model belongs to the Neuro-SM model with the output mapping [13]. While N _v > 0, then the general Neuro-SM model without the output mapping is the dynamic Neuro-SM model [14]. In this way, the proposed general Neuro-SM generalizes the previously published Neuro-SM technique. Furthermore, while N _v > 0 and N _c > 0, a new Neuro-SM technique is presented for the first time. Compared to the Neuro-SM introduced in [10, 13, 14], the new Neuro-SM is more suitable for modeling the microwave devices with high order dynamics and nonlinearity due to inclusion of dynamic mapping as well as current mapping.

The general Neuro-SM model will not be accurate unless the dynamic voltage and dynamic current mapping neural networks are trained suitable. In order to train the general Neuro-SM efficiently with typical types of transistor modeling data, the relationship between the dynamic voltage and current mapping neural networks with typical types of transistor data, such as DC, bias-dependent S parameter, and large-signal harmonic data need to be derived.

Let the number of hidden neurons of the dynamic voltage and current mapping neural networks be N_hv and N_hc, respectively. Let generic symbols w_{1, i} (i = 1, 2, …,  N_hv) and w_{2, i} (i = 1, 2, …, N_hc) be internal weights of the voltage and current mapping neural network, respectively. w_{1, i} and w_{2, i} are the i-th component of vectors w₁ and w₂, respectively. In order to train the general Neuro-SM efficiently, gradient information provided by sensitivities of the model with respect to w_{1, i} and w_{2, i} is needed [16].

Let x be a generic variable in the coarse model. In case the coarse model parameter needs to be treated as a variable in circuit optimization, it is useful to obtain the sensitivity for DC, bias-dependent S parameter, and large-signal HB responses of the general Neuro-SM model due to changes in the generic optimization variable x.

In this phase, the weights of dynamic voltage and current mapping neural networks, i.e., w ₁ and w ₂ , are trained such that the overall training error of the general Neuro-SM model can be reduced to satisfy the specifications. The overall training error for combined DC, small-signal S parameter, and large-signal HB training is defined as the total difference between all nonlinear device data and the general Neuro-SM model as:

$$ {\displaystyle \begin{array}{l}E\left({\boldsymbol{w}}_{\boldsymbol{1}},{\boldsymbol{w}}_{\boldsymbol{2}}\right)=\frac{1}{2}\sum \limits_{k=1}^{N_{V_{f2}}}\sum \limits_{l=1}^{N_{V_{f1}}}{\left\Vert \boldsymbol{A}\cdot \left(\boldsymbol{I}\left({V}_{Gl},{V}_{Dk},{\boldsymbol{w}}_{\boldsymbol{1}},{\boldsymbol{w}}_{\boldsymbol{2}},\right)-{\boldsymbol{I}}_{Dl}^k\right)\right\Vert}^2\\ {}\kern1.6em +\frac{1}{2}\sum \limits_{k=1}^{N_{V_{f2}}}\sum \limits_{l=1}^{N_{V_{f1}}}\sum \limits_{j=1}^{N_{\mathrm{freq}}}{\left\Vert \boldsymbol{B}\cdot \left(\boldsymbol{S}\left({V}_{Gl},{V}_{Dk},{\omega}_j,{\boldsymbol{w}}_{\boldsymbol{1}},{\boldsymbol{w}}_{\boldsymbol{2}}\right)-{\boldsymbol{S}}_{Dl j}^k\right)\right\Vert}^2\kern5.999997em \\ {}\kern1.1em +\frac{1}{2}\sum \limits_{k=1}^{N_{V_{f2}}}\sum \limits_{l=1}^{N_{V_{f1}}}\sum \limits_{m=1}^{N_H}\sum \limits_{n=1}^{N_P}{\left\Vert \boldsymbol{C}\cdot \left(\boldsymbol{HB}\left({V}_{Gl},{V}_{Dk},{\omega}_m,{P}_n,{\boldsymbol{w}}_{\boldsymbol{1}},{\boldsymbol{w}}_{\boldsymbol{2}}\right)-{\boldsymbol{HB}}_{Dk l}^{mn}\right)\right\Vert}^2\end{array}} $$

(19)

where I(.), S(.), and HB(.) are the DC, bias-dependent S parameter, and HB responses of the general Neuro-SM model, respectively. Take FET modeling as an example, vector I(.) contains gate and drain current I_f1 and I_f2, which can be computed by Eq. (3). Vector S(.) is achieved from the Y matrix defined by Eq. (5). HB responses of the general Neuro-SM model, i.e., HB(.) can be calculated by Eq. (7). I _D , S _D , and HB _D represent the DC current, small-signal S parameter, and large-signal HB responses of the modeling device, respectively. The subscript k \( \left(k=1,2,\dots, {N}_{V_{f2}}\right) \), l \( \left(l=1,2,\dots, {N}_{V_{f1}}\right) \), j (j = 1, 2, …, N_freq), m (m = 1, 2, …, N _H ), and n (n = 1, 2, …, N _P ) denote the indices of V_f2, V_f1, frequency, harmonic frequency, and input power level, respectively. \( {N}_{V_{f1}} \), \( {N}_{V_{f2}} \), N_freq, N _H , and N _P are the total number of V_f1, V_f2,frequency, harmonic frequency, and input power level, respectively. Diagonal matrices A, B, and C contain all the scaling factors, which are defined as the inverse of the minimum-to-maximum range of the I _D data, S _D data, and HB _D data, respectively. The training error calculation of the general Neuro-SM model for combined DC and S parameter training as well as HB training further illustrates in Fig. 2. Figure 2a, b is error calculation for combined dc and small-signal S parameter training as well as large-signal HB training, respectively.

The objective of the model training is to minimize the error E defined in (19) by optimizing w ₁ and w ₂ . In general, gradient-based training algorithm is used. After training, the general Neuro-SM model with appropriate hidden neurons and delay buffers can accurately represent the nonlinear behavior of the modeling device.

The proposed Neuro-SM model, after being trained for a specific range, is very good at representing the nonlinear behavior of the microwave device within the training region. However, when we use model in a wider range than the training range, inappropriate derivative information of the model outside the training range may mislead the iterative process into slow convergence or even divergence during large-signal simulation. One possible way to solve the divergence problem is to use appropriate extrapolation technique. For general Neuro-SM technique, a simple and effective extrapolation technique is used to improve the convergence of the model [18].

For simplification, the proposed general Neuro-SM technique is formulated for 2-port field-effect transistor (FET) modeling. This approach can be further extended to n-port network, where all the notations and equations are extended accordingly. After the generalization, the proposed general Neuro-SM technique has the potential to be used for developing models of microwave devices with trapping effect.

The format of the general Neuro-SM model presented so far is to map the voltage input signals between the coarse and fine models. Hence, our approach presented so far is applicable to modeling voltage controlled devices, such as FET and HEMT. It is possible to extend the method to a mixed input mapping case, where the dynamic input mappings are for a mixture of port voltage and current signals. In that way, our approach can be extended to modeling current controlled devices, such as HBT.

The frequency limit of the proposed general Neuro-SM model depends on the frequency limit of training data. For example, if the frequency in the training data extends to millimeter wave bands, the proposed general mapping will be even more important because of the need of capacitive effects, non-quasi-static effects, and nonlinear effects in the model. In this case, more hidden neurons and time delay buffers maybe needed to guarantee the accuracy of the proposed general Neuro-SM model.

This example illustrates the use of the general Neuro-SM for modeling of a real 2 × 50 μm GaAs pHEMT device. The training and test data is obtained from measurement. An enhanced Angelov model including a thermal subcircuit to model the self-heating effect of the device proposed in [19] is used as the existing coarse model. Even though parameters in enhanced Angelov model are extracted as much as possible, there are still distinct differences between the model and measured data. Thus, Neuro-SM is used to bridge the gap between the coarse model and measured data. We then apply the previously published Neuro-SM technique such as Neuro-SM with the output mapping [13] and dynamic Neuro-SM [14] to get more accurate models. After training, the accuracy of the two Neuro-SM models is clearly improved compared to that of the coarse model, as shown in Fig. 3. However, the previous Neuro-SM techniques at their best are still insufficient to achieve the desired accuracy. Then, our proposed general Neuro-SM is used to get a more accurate model.

Training was firstly done in NeuroModelerPlus [20] using DC and bias-dependent S parameter data for 400 iterations. Then, training refinement was done using combined DC, bias-dependent S parameter, and HB data at 189 different biases for 3600 iterations. Harmonic data used for HB training was measured at 7.5 GHz fundamental frequency and different input power levels (− 10~ 3 dBm). Time delay parameters are both 0.008 ns. The number of hidden neurons for both voltage and current mapping neural networks is 30.

After training, we compared the DC, bias-dependent S parameter, and large-signal HB responses of the pHEMT device with those computed from the coarse model, Neuro-SM with the output mapping [13], dynamic Neuro-SM [14] with 5 delay buffers and 30 hidden neurons, and the proposed general Neuro-SM model with 5 delay buffers and 30 hidden neurons both for dynamic voltage and current mapping neural networks as shown in Fig. 3. In Fig. 3a, b–e, f represent the comparisons of dc, S parameter at two test bias points (0.7 V, 2.4 V) and (0.3 V, 5.2 V), as well as HB responses at different input power levels (− 10~ 3 dBm), respectively. As observed from Fig. 3, the responses computed from the proposed general Neuro-SM are closest to the data among all the four models in this comparison. We obtain further improvement in model accuracy using general Neuro-SM technique because additional and useful degrees of freedom provided by the new dynamic current mappings at the gate and the drain in the general model. The increased accuracy of the general Neuro-SM model helps to improve the accuracy of circuit and system simulation, such as simulation to predict power performance and linearity of high-frequency PA designs.

The proposed general Neuro-SM model can be conveniently implemented into the existing circuit simulators such as Keysight ADS for high-level circuit and system design. Figure 4 shows the proposed general Neuro-SM model structure in ADS. The time delay parameter is 0.08 ns. In this figure, the dynamic voltage mapping neural networks are embedded as the functions in two 7-port symbolically defined devices (SDDs), i.e., SDD7P1, and SDD7P2. Similarly, the dynamic current mapping neural networks are embedded as the functions in two 9-port SDDs, i.e., SDD9P1 and SDD9P2. Time delay voltage and current signals can be obtained using voltage controlled voltage sources with delay parameters, i.e., SRC1~SRC8. After implementing the general Neuro-SM model into ADS, we have also compared simulation speed between coarse model, dynamic Neuro-SM, and the proposed general Neuro-SM model on an Intel i5-3230M 2.6 GHz computer as shown in Table 2. The simulation was performed by Monte Carlo analysis of 200 HB simulations. As seen in Table 2, the simulation time is 48.32 s using coarse model, compared to 57.17 s using general Neuro-SM, showing that the simulation speed of the proposed general Neuro-SM is acceptable in view of its good accuracy.

Model type	HB simulation
Coarse model	48.32 s
Dynamic Neuro-SM	54.23 s
The proposed Neuro-SM model	57.17 s

This paper has presented a general Neuro-SM technique for nonlinear device modeling. By modifying the dynamic current and dynamic voltage relationships in the existing coarse model, the proposed general Neuro-SM model can exceed the accuracy limit over the coarse model, the Neuro-SM model with the output mapping, and the dynamic Neuro-SM model. Compared to previously published Neuro-SM, the proposed general Neuro-SM has demonstrated much improved performance in terms of accuracy by a pHEMT modeling example. The general Neuro-SM model can be applied to microwave circuit and system design.