- Research
- Open Access
Dynamic voltage and frequency scaling scheme for an adaptive LDPC decoder using SNR estimation
- Youngho Ahn^{1},
- Joo-yul Park^{1} and
- Ki-Seok Chung^{1}Email author
https://doi.org/10.1186/1687-1499-2013-255
© Ahn et al.; licensee Springer. 2013
- Received: 5 December 2012
- Accepted: 17 October 2013
- Published: 1 November 2013
Abstract
In this paper, we propose a low-power adaptive low-density parity check (LDPC) decoder that utilizes dynamic voltage and frequency scaling to reduce power consumption. Most existing adaptive LDPC decoders have focused only on the decoding performance based on the signal-to-noise ratio (SNR) estimation. However, significant idle power is consumed when the decoder awaits the next frame after processing a frame. In mobile communication standards such as China Mobile Multimedia Broadcasting and Digital Video Broadcasting Satellite Second Generation, adaptive coding and modulation has been adopted. Thus, it is possible to reduce the power consumption efficiently by using the SNR estimation. In this paper, we apply a customized frequency selection scheme and a variable voltage generation scheme to an adaptive LDPC decoder to reduce the dynamic power consumption. The proposed schemes result in a reduction of 44% in the energy consumption of an LDPC decoder implemented using 0.18-μm complementary metal-oxide-semiconductor technology.
Keywords
- LDPC decoder
- SNR estimation
- DVFS
1 Introduction
Today, the need for a reliable high transmission rate is increasing in order to offer various multimedia services with 4G mobile communication systems. Since data transmission in mobile circumstances with a data rate requirement of more than 100 Mbps is common, the demand for efficient error correction codes has been rapidly growing. Turbo codes were regarded as the best channel coding method before low-density parity check (LDPC) codes started to draw attention. Because LDPC codes have a larger minimum distance than Turbo codes and exhibit very good bit error rate (BER) curves, LDPC codes are being studied actively in the area of next-generation data communication [1].
LDPC codes are linear block codes that were originally devised by Gallager in the 1960s [2]. However, the codes were impossible to implement in hardware in those days, so they were largely ignored. About 30 years later, Mackay and Neal reviewed the LDPC code, and they rediscovered the excellent properties of the code thanks to the development of communication and integrated circuit technologies [3]. In 2001, Chung and Richardson showed that the LDPC code can approach within 0.0045 dB of the Shannon limit [4]. Many iterative LDPC decoding schemes are based on the Sum-Product algorithm [5] because the algorithm can be fully parallelized, resulting in high-speed decoding [6]. LDPC codes have been adopted by mobile communication standards such as China Mobile Multimedia Broadcasting (CMMB) [7] and Digital Video Broadcasting Satellite Second Generation (DVB-S2) [8].
There are several studies for low-power LDPC decoding, and they are based on the fact that the dynamic power consumption of a module is proportional to the amount of switching activity. In [9, 10], adjusting either the maximum number of iterations or the quantization level according to the estimated SNR value is proposed in order to reduce the decoding power consumption. In [11], it was shown that dynamic voltage and frequency scaling (DVFS) could be effective in reducing the power consumption while maintaining the BER performance of an LDPC decoder. The number of parity-check errors after a predetermined number of iterations is used to estimate the remaining number of iterations until decoder termination and is used to determine the voltage and the clock frequency for the remaining iterations. Unlike the previous works, the estimated SNR value in this paper is considered to determine the supply voltage and the operating frequency of an LDPC decoder. The SNR estimator using a pilot signal has been employed in adaptive coding and modulation (ACM) [8] for DVB-S2. Thus, the proposed DVFS scheme can be applied to such standards with negligible overhead.
In this paper, binary LDPC codes for CMMB over an additive white Gaussian noise (AWGN) channel with BPSK modulation are considered. We determine the correlation between the throughput and the power consumption of an LDPC decoder with respect to the channel SNR. In DVFS schemes, the supply voltage control is crucial since the achievable maximum clock speed of the circuits is dependent on the supply voltage level. For example, if the maximum clock speed generated by the supply voltage is lower than the required operating clock frequency, a timing violation may occur. To apply the proposed DVFS scheme to an LDPC decoder, we designed a DVFS controller composed of a frequency selector and a supply voltage generator. A look-up table is used for the frequency selector, and the supply voltage generator is based on the variable supply voltage scheme suggested in [12]. Various performance evaluations were conducted to make sure that slowing the performance through DVFS would not violate the throughput requirement of the CMMB standard. With the addition of the controller, the size is increased by 2.2%, while the power consumption is reduced by up to 44% for CMMB codes. Our contributions for low-power LDPC decoding are summarized as follows. First, we show that we can increase the power efficiency of the LDPC decoding with negligible area overhead since almost all of the ACM schemes employ a hardware module for the SNR estimation. Second, we show the power savings when a DVFS scheme is used for standard code such as CMMB. Third, the proposed DVFS scheme can be applied to any standard because the proposed DVFS controller is independent of specific ACM structures. Finally, the proposed LDPC decoder is the design of an ASIC decoder including a DVFS controller, and we used commercial tools to evaluate the quality of the proposed LDPC decoder.
This paper consists of five sections. In the following section, we address the theoretical background regarding LDPC decoding, including the main characteristics of an adaptive LDPC decoder and the conventional structure of the ACM decoding flow. In Section 3, we find the operating clock frequency that satisfies the throughput requirement of CMMB and generate the supply voltage for the required operating clock frequency. The implementation and experimental results are presented in Section 4, and Section 5 concludes this paper.
2 Background
2.1 LDPC decoding algorithm
LDPC decoding based on log likelihood ratio (LLR) belief propagation (BP) algorithm
Definition | LDPC decoding |
---|---|
H _{ mn } | the value at row m and col n of H-matrix |
N(m) | the set of bit nodes including the check node m |
M(n) | the set of check nodes including the bit node n |
Algorithm | |
Initialization | set F_{ n } = LLR for bit nodes (n = 1,2,…,N) |
set Z_{ mn } = F_{ n } if H_{ mn } is 1 for each (m,n) | |
while (i ≤ i_{max}) | |
Check node | for each check node |
Processing | where each (m,n) if H_{ mn } is 1 |
${T}_{\mathit{mn}}={\displaystyle \prod _{{n}^{\prime}\in N\left(m\right)\backslash \left\{n\right\}}}\frac{1-{e}^{{Z}_{m{n}^{\prime}}}}{1+{e}^{{Z}_{m{n}^{\prime}}}}$ | |
${L}_{\mathit{mn}}=\mathit{ln}\frac{1-{T}_{\mathit{mn}}}{1+{T}_{\mathit{mn}}}$ | |
end for | |
Bit node | for each bit node |
Processing | where each (m,n) if H_{mn} is 1 |
${Z}_{\mathit{mn}}={F}_{n}+{\displaystyle \sum _{{m}^{\prime}\in M\left(n\right)\backslash \left\{m\right\}}}{L}_{{m}^{\prime}n}$ | |
${Z}_{n}={F}_{n}+{\displaystyle \sum _{m\in M\left(n\right)}}{L}_{\mathit{mn}}$ | |
end for | |
Tentative | for each n (n = 1,2,…,N) |
Decision | $\widehat{C}=\left[\begin{array}{ccc}\hfill {\widehat{C}}_{1}\hfill & \hfill \cdots \hfill & \hfill {\widehat{C}}_{N}\hfill \end{array}\right],{\widehat{C}}_{n}=\left\{\begin{array}{cc}\hfill 0,\hfill & \hfill {Z}_{n}\ge 0\hfill \\ \hfill 1,\hfill & \hfill {Z}_{n}<0\hfill \end{array}\right.$ |
end for | |
Parity check | if ${H}^{2}{\left[\begin{array}{ccc}\hfill {\widehat{C}}_{1}\hfill & \hfill \cdots \hfill & \hfill {\widehat{C}}_{N}\hfill \end{array}\right]}^{T}$ is 0 |
return success | |
i ++ | |
end while |
2.2 Adaptive coding and modulation
2.3 Dynamic voltage and frequency scaling
where P_{switching} is the dynamic power consumption due to switching activities, P_{SC} is the dynamic power consumption due to the short circuit current (I_{SC}), and P_{leakage} is the static power consumption due to the leakage current. The value of P_{switching} is proportional to the operation frequency and the square of the supply voltage, since the voltage change ΔV is approximately equal to the supply voltage, V_{dd}. In the equation for P_{switching}, α and C_{ L } are constant, and they represent the node transition factor and the loading capacitance, respectively. Hence, DVFS is very effective in reducing P_{switching}. DVFS has been commonly used to reduce the dynamic power consumption of both high-performance desktop CPUs and mobile embedded CPUs. In this paper, we apply DVFS to reduce the power consumption of LDPC decoders by adding a DVFS controller to dynamically determine the proper level of the supply voltage and the corresponding operating frequency.
3 Proposed low-power LDPC decoder
3.1 Adaptive low-power LDPC decoder
Number of iterations versus SNR value (CMMB r = 1/2, max iteration: 50, frame: 1,000,000)
SNR | Iteration # | ||
---|---|---|---|
Min | Max | Avg | |
-1 | 50 | 50 | 50 |
-0.5 | 50 | 50 | 50 |
0 | 50 | 50 | 50 |
0.5 | 50 | 50 | 50 |
1 | 42 | 50 | 49.88 |
1.5 | 10 | 50 | 21.51 |
2 | 6 | 19 | 10.94 |
2.5 | 4 | 11 | 7.75 |
3 | 4 | 9 | 6.03 |
3.5 | 4 | 7 | 4.91 |
4 | 3 | 6 | 4.1 |
4.5 | 2 | 5 | 3.45 |
5 | 2 | 4 | 3.02 |
5.5 | 2 | 4 | 2.6 |
6 | 2 | 4 | 2.16 |
6.5 | 1 | 3 | 2.02 |
7 | 1 | 3 | 1.86 |
7.5 | 1 | 3 | 1.48 |
8 | 1 | 2 | 1.16 |
8.5 | 1 | 2 | 1.04 |
9 | 1 | 2 | 1.01 |
9.5 | 1 | 2 | 1 |
10 | 1 | 2 | 1 |
10.5 | 1 | 2 | 1 |
11 | 1 | 1 | 1 |
11.5 | 1 | 1 | 1 |
12 | 1 | 1 | 1 |
12.5 | 1 | 1 | 1 |
3.2 Frequency scaling scheme based on SNR estimation
Minimum operating frequency to iteration number satisfying CMMB throughput (CMMB r = 1/2)
Max iteration # | Throughput (Mbps) | Operating clock (MHz) |
---|---|---|
26 | 11.10 | 185 |
25 | 10.29 | 165 |
24 | 10.71 | 165 |
23 | 11.16 | 165 |
22 | 10.24 | 145 |
21 | 10.71 | 145 |
20 | 11.23 | 145 |
19 | 10.18 | 125 |
18 | 10.73 | 125 |
17 | 11.34 | 125 |
16 | 10.10 | 105 |
15 | 10.74 | 105 |
14 | 11.48 | 105 |
13 | 9.98 | 85 |
12 | 10.77 | 85 |
11 | 11.70 | 85 |
10 | 9.79 | 65 |
9 | 10.81 | 65 |
8 | 12.06 | 65 |
7 | 9.45 | 45 |
6 | 10.88 | 45 |
5 | 12.83 | 45 |
4 | 8.67 | 25 |
3.3 Variable supply voltage generator
4 Experimental results
Synthesis results
Technology | Charted 0.18-μm CMOS |
---|---|
LDPC total (in NAND2) | 316 K |
Check node (in NAND2) | 154 K |
Bit node (in NAND2) | 13 K |
AGU (in NAND2, with memory) | 82 K |
SNR estimator (in NAND2) | 31 K |
Parity check (in NAND2) | 1 K |
Tentative (in NAND2) | 1 K |
Critical Path Replicas (in NAND2) | 7 K |
Operating freq. (MHz) | 45 to 185 |
Voltage (V) | 0.9 to 1.8 |
Operating frequency and supply voltage scheme based on SNR estimation (CMMB r = 1/2)
SNR (dB) | Frequency (MHz) | Voltage (V) |
---|---|---|
1.5 | 185 | 1.8 |
2.0 | 145 | 1.5 |
2.5 | 85 | 1.1 |
3.0 | 85 | 1.1 |
3.5 | 65 | 1.0 |
4.0 | 65 | 1.0 |
4.5 | 45 | 0.9 |
5.0 | 45 | 0.9 |
5.5 | 45 | 0.9 |
6.0 | 45 | 0.9 |
5 Conclusion and future work
In this paper, we proposed a low power LDPC decoder for China Mobile Multimedia Broadcasting (CMMB) that utilizes DVFS. The proposed decoder consists of an adaptive LDPC decoder and a DVFS controller. The design has a partially parallel structure with 16 sets of processing units to satisfy the throughput requirement of CMMB and operates adaptively according to the SNR estimation. Based on the observation that the maximum decoding iteration counts differ according to the SNR values, we obtained the set of operating frequencies and supply voltage levels for which the proposed decoder would operate to satisfy the throughput requirement of the CMMB standard. A DVFS controller was added to the design to adjust the clock frequency and the supply voltage level, but the area and overhead in terms of the power consumption due to the controller turned out to be negligibly small, 2.3 and 0.002%, respectively. For SNR values greater than 2 dB, the power consumption was reduced by up to 44%, and we showed that the LDPC decoder for CMMB using DVFS becomes even more power-efficient as the SNR value increases from 1.5 to 4 dB. Our future works include methods for more accurate SNR estimation for finer-grained DVFS control.
Declarations
Acknowledgments
This research was supported by the MSIP (Ministry of Science, ICT & Future Planning), Korea, under the ITRC (Information Technology Research Center) support program supervised by the NIPA (National IT Industry Promotion Agency) (NIPA-2013-H0301-13-1011).
Authors’ Affiliations
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This article is published under license to BioMed Central Ltd. This is an open access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.